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PDF LC70310KBG Data sheet ( Hoja de datos )
| Número de pieza | LC70310KBG | |
| Descripción | Noise Canseller IC | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Ordering number : ENA1539A
LC70310KBG
CMOS LSI
Noise Canseller IC
http://onsemi.com
Overview
The LC70310KBG is a noise-cancellation IC that uses an original digital signal processor (DSP) designed for audio
applications as the core and integrates the serial PCM interface and host CPU interface on a single chip. In addition,
by incorporating an audio signal processing program using our company’s unique noise-cancelling algorithm, it
features a significantly improved noise-cancelling accuracy.
While reducing the noise components to one-tenth or less, the IC is still capable of maintaining the quality of the
sound with no loss of its naturalness.
The LC70310KBG also makes it possible to provide filter processing and other such operations alongside the
noisecancelling function.
The PCM interface supports the I2S mode and enables stereo sound processing.
Features
(1) DSP block
• 16-bit DSP core
• Noise-cancellation processing, filter processing
• Power-save mode (oscillation stop, PLL stop, switching between high-speed operation and low-speed operation)
(2) Host CPU interface (4-line system or I2C bus* format): Slave (also used as GPIO0 to 3, GPIO13 to 14)
(3) Serial PCM interface (4-line system) : 2 systems of master and slave (also used as GPIO4 to 7, GPIO10 and 11)
• I2S, left justified, long frame synchronization, short frame synchronization: Fs=8 kHz supported in master mode
(4) GPIO: 16 ports (also used as host CPU interface and serial PCM interface)
(5) Package: FBGA64K (5mm × 5mm)
(6) Power supplies (supply voltages) : 2 power sources. 2.85V: 2.7V to 3.6V (IO, XVDD), 1.2V±10% (internal logic)
Package
FBGA64K(5mm 5mm)
FBGA64K
Figure 1
ORDERING INFORMATION
See detailed ordering and shipping information on page 48 of this data sheet.
Semiconductor Components Industries, LLC, 2013
November, 2013
N2013HK 20090722-S00002 No.A1539-1/48
1 page  
LC70310KBG
XVDD ≥ CVDD1 to 4 > DVDD1 to 3 = PLLVDD
Table 1 (b) IO Attribute Symbols
IO Attribute
DI
DIS
DO
DB
DBS
AI
AO
Power supply
NC
Description
Digital input
Digital input (Schmidt input)
Digital output
Digital input / output
Digital input / output (Schmidt input)
Analog input
Analog output
Power supply / GND
No connection
No.A1539-5/48
5 Page 
LC70310KBG
(1-2) Procedure for program data transfer using 4-line interface
The host CPU confirms that the BUSY signal is “H,” outputs “L” to the BUSY pin (open drain pin), and then starts
transferring the program data to the LC70310. The program data is transferred in 6-word units (18 bytes) with the MSB
first.
After transferring the first 6 words, the host CPU returns the BUSY pin to “H.” In response, the LC70310 executes the
internal processing. At this time, the LC70310 sets the BUSY pin to “L,” and informs the host CPU that processing is in
progress. The host CPU confirms that the BUSY pin has been set to “H,” and starts transferring the next 6 words. It
repeats this transfer up to the end address of the program. (Refer to Figure. 7(a).)
When the host CPU completes the transfer of the last 6 words and sets the BUSY pin to “H,” the LC70310 executes
the internal processing, and then it automatically executes the program from address 0. (Refer to Figure 7(b).)
SCK
(GPIO1)
SI
(GPIO0)
BUSY
(GPIO3)
Boot start
D0 D0
23 22
0.4us or longer
Data transfer is repeated between these two points
D0 D0 D1 D1
1 0 23 22
D3 D3 D4 D4
1 0 23 22
D5 D5
10
Figure 7(a)
D0 D0
23 22
SCK
(GPIO1)
SI D0 D0
(GPIO0) 23 22
BUSY
(GPIO3)
D0 D0 D1 D1
1 0 23 22
D3 D3 D4 D4
1 0 23 22
Figure 7(b)
End of transfer
Program start
D5 D5
10
0.9 ~ 1.1 [μs]
CPU side access
DSP side access
No.A1539-11/48
11 Page | ||
| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet LC70310KBG.PDF ] | |
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