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Número de pieza | HD74HC112 | |
Descripción | Dual J-K Flip-Flops (with Preset and Clear) | |
Fabricantes | Hitachi Semiconductor | |
Logotipo | ||
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No Preview Available ! HD74HC112
Dual J-K Flip-Flops (with Preset and Clear)
Description
Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is
edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear
and preset are independent of the clock and accomplished by a low logic level on the corresponding input.
Features
• High Speed Operation: tpd (Clock to Q) = 17 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
Function Table
Inputs
Output
Preset
Clear
Clock
J
K
Q
Q
LH X X X H L
HL X X X L H
L L X X X H*1 H*1
HH
L L No Change
HH
L HL H
HH
HL H L
HH
H H Toggle
HH
L
X X No Change
H H H X X No Change
H
Note:
H X X No Change
1. Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable,
if Preset and Clear go HIGH simultaneously.
1 page 19.20
20.00 Max
16
9
1
1.3
1.11 Max
8
Unit: mm
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25
+
–
0.13
0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
DP-16
Conforms
Conforms
1.07 g
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet HD74HC112.PDF ] |
Número de pieza | Descripción | Fabricantes |
HD74HC11 | Triple 3-input AND Gates | Hitachi Semiconductor |
HD74HC112 | Dual J-K Flip-Flops (with Preset and Clear) | Hitachi Semiconductor |
HD74HC113 | Dual J-K Flip-Flops (with Preset) | Hitachi Semiconductor |
HD74HC114 | Dual J-K Flip-Flops (with Preset/ Common Clear and Common Clock) | Hitachi Semiconductor |
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