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HD74CDCV857 fiches techniques PDF

Hitachi Semiconductor - 2.5-V Phase-lock Loop Clock Driver

Numéro de référence HD74CDCV857
Description 2.5-V Phase-lock Loop Clock Driver
Fabricant Hitachi Semiconductor 
Logo Hitachi Semiconductor 





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HD74CDCV857 fiche technique
HD74CDCV857
2.5-V Phase-lock Loop Clock Driver
ADE-205-335C (Z)
Preliminary
4th Edition
March 2000
Description
The HD74CDCV857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is
specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.
Features
Supports 60 MHz to 200 MHz operation range
Distributes one differential clock input pair to ten differential clock outputs pairs
Supports spread spectrum clock requirements meeting the PC100 SDRAM registered DIMM
specification
External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input
Supports 2.5V analog supply voltage (AVCC), and 2.5 V VDDQ
No external RC network required
Sleep mode detection
48pin TSSOP (Thin Shrink Small Outline Package)

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