PDF HD74CDC857 Data sheet ( Hoja de datos )

Número de pieza	HD74CDC857
Descripción	3.3/2.5-V Phase-lock Loop Clock Driver
Fabricantes	Hitachi Semiconductor
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No Preview Available ! HD74CDC857 3.3/2.5-V Phase-lock Loop Clock Driver ADE-205-222E (Z) 6th. Edition July 1999 Description The HD74CDC857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is specifically designed for use with DDR (Double Data Rate) synchronous DRAMs. Features • Supports 100 MHz to 150 MHz operation range 1 • Distributes one differential clock input pair to ten differential clock outputs pairs • SSTL_2 (Stub Series Terminated Logic) differential inputs and LVCMOS reset (G) input • Supports spread spectrum clock • External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input • Supports both 3.3 V/2.5V analog supply voltage (AVCC), and 2.5 V VDDQ • No external RC network required • Sleep mode detection • 48pin TSSOP (Thin Shrink Small Outline Package) Note: 1. 200 MHz (Max) ver. will be available by 4Q/’99 Function Table Inputs G CLK CLK LLH L HL HL H HHL X 0 MHz 0 MHz H : High level L : Low level Z : High impedance X : Don’t care : : : : : : : Outputs YY ZZ ZZ LH HL ZZ FBOUT Z Z L H Z FBOUT Z Z H L Z : : : : : : PLL off off run run off 1 page VTR VCP CLK CLK VID Crossing point Figure 1-1 Differential input levels HD74CDC857 VDDQ GND VDDQ Vref4 GND Figure 1-2 Single input levels CLK CLK Vref 5 5 Page Package Dimensions 12.50 +0.3 –0.1 48 25 1 0.20 +0.1 –0.05 24 0.50 0.08 M 0.65 Max 0.10 HD74CDC857 Unit : mm 8.10 ± 0.3 10° Max 0.50 ± 0.1 Hitachi code EIAJ code JEDEC code TTP-48DC — — 11 11 Page

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Número de pieza	Descripción	Fabricantes
HD74CDC857	3.3/2.5-V Phase-lock Loop Clock Driver	Hitachi Semiconductor

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