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PDF HD74BC244A Data sheet ( Hoja de datos )

Número de pieza HD74BC244A
Descripción Octal Buffers/Line Drivers With 3 State Outputs
Fabricantes Hitachi Semiconductor 
Logotipo Hitachi Semiconductor Logotipo



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No Preview Available ! HD74BC244A Hoja de datos, Descripción, Manual

HD74BC244A
Octal Buffers/Line Drivers With 3 State Outputs
ADE-205-007A (Z)
2nd. Edition
March 1993
Description
The HD74BC244A provides high drivability and operation equal to or better than high speed bipolar
standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5
of high speed bipolar logic IC, when the frequency is 10 MHz. The device has eight inverter drivers with
three state outputs in a 20 pin package. This device is a non inverting buffer and has two active low
enables (1G and 2G). Each enable independently controls 4 buffers.
Features
Input/Output are at high impedance state when power supply is off.
Built in input pull up circuit can make input pins be open, when not used.
TTL level input
Wide operating temperature range
Ta = –40 to + 85°C
Function Table
Inputs
G
H
L
L
H : High level
L : Low level
X : Immaterial
Z : High impedance
A
X
H
L
Output Y
Z
H
L

1 page




HD74BC244A pdf
Switching Test Method (CL = 50 pF)
Item
Propagation delay time
Output enable time
Output disable time
Input capacitanse
Output capacitance
Symbol
Ta = 25°C
VCC = 5.0 V
Min Max
tPLH 3.0 6.0
tPHL 3.0 6.0
tZH 3.0 8.0
tZL 3.0 8.0
tHZ 3.0 7.0
tLZ 3.0 7.0
CIN 3.0(Typ)
CO 15.0(Typ)
HD74BC244A
Ta = –40 to 85°C
VCC = 5.0 V ±10%
Min Max
3.0 7.0
3.0 7.0
3.0 10.0
3.0 10.0
3.0 9.0
3.0 9.0
Unit Test Conditions
ns See under figure
ns
ns
pF VIN = VCC or GND
pF VO = VCC or GND
Test Circuit
VCC
Input
Pulse Generator
Zout = 50
VCC
Output
G
1Y1
1A1
1A2
500
CL =
50 pF
450
50 Scope
Output
1A3
1Y2
Same as above
load circuit
1A4
1Y3
Same as above
load circuit
1Y4
Same as above
load circuit
Notes:
1. CL includes probe and jig capacitance.
2. 2G, 2A1-2A4 to 2Y1-2Y4 are identical to above load circuit.
2. Open: tPLH, tPHL, tZH, tHZ
7 V: tZL, tLZ
*3
OPEN
7V
5

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