C8051F921 Datasheet PDF - Silicon Laboratories
| Part Number | C8051F921 | |
| Description | 10-Bit ADC MCU | |
| Manufacturers | Silicon Laboratories | |
| Logo |  |
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There is a preview and C8051F921 download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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C8051F93x-C8051F92x
Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU
Supply Voltage 0.9 to 3.6 V
- One-Cell Mode supports 0.9 to 1.8 V operation
- Two-Cell Mode supports 1.8 to 3.6 V operation
- Built-in dc-dc converter with 1.8 to 3.3 V output for
use in one-cell mode
- Built-in LDO regulator allows a high analog supply
voltage and low digital core voltage
- 2 built-in supply monitors (brownout detectors)
10-Bit Analog to Digital Converter
- ±1 LSB INL; no missing codes
- Programmable throughput up to 300 ksps
- Up to 23 external inputs
- On-Chip Voltage Reference
- On-Chip PGA allows measuring voltages up to twice
the reference voltage
- 16-bit Auto-Averaging Accumulator with Burst Mode
provides increased ADC resolution
- Data dependent windowed interrupt generator
- Built-in temperature sensor
Two Comparators
- Programmable hysteresis and response time
- Configurable as wake-up or reset source
- Up to 23 Capacitive Touch Sense Inputs
6-Bit Programmable Current Reference
- Up to ±500 µA. Can be used as a bias or for
generating a custom reference voltage
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 4352 bytes internal data RAM (256 + 4096)
- 64 kB (‘F93x) or 32 kB (‘F92x) Flash; In-system pro-
grammable in 1024-byte sectors—1024 bytes are
reserved in the 64 kB devices
Digital Peripherals
- 24 or 16 port I/O; All 5 V tolerant with high sink
current and programmable drive strength-
- Hardware SMBus™ (I2C™ Compatible), 2 x SPI™,
and UART serial ports available concurrently
- Four general purpose 16-bit counter/timers
- Programmable 16-bit counter/timer array with six
capture/compare modules and watchdog timer
- Hardware SmaRTClock operates down to 0.9 V and
requires less than 0.5 µA supply current
Clock Sources
- Internal oscillators: 24.5 MHz, 2% accuracy
supports UART operation; 20 MHz low power
oscillator requires very little bias current
- External oscillator: Crystal, RC, C, or CMOS Clock
- SmaRTClock oscillator: 32 kHz Crystal or internal
self-oscillate mode
- Can switch between clock sources on-the-fly; useful
in implementing various power saving modes
Packages
- 32-pin QFN (5 x 5 mm)
- 24-pin QFN (4 x 4 mm)
- 32-pin LQFP (7 x 7 mm, easy to hand-solder)
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
A 10-bit
M
U
X
300 ksps
ADC
IREF
++
TEMP VREF –
–
SENSOR VREG VOLTAGE
COMPARATORS
DIGITAL I/O
UART
SMBus
Port 0
2 x SPI
PCA
Timer 0
Port 1
Timer 1
Timer 2
Timer 3
Port 2
CRC
24.5 MHz PRECISION
INTERNAL OSCILLATOR
20 MHz LOW POWER
INTERNAL OSCILLATOR
External Oscillator
HARDWARE SmaRTClock
HIGH-SPEED CONTROLLER CORE
64/32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
4352 B
SRAM
POR WDT
Rev. 1.4 11/13
Copyright © 2013 by Silicon Laboratories
C8051F93x-C8051F92x
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C8051F93x-C8051F92x
13.1.3.Flash Write Procedure ........................................................................... 149
13.2.Non-volatile Data Storage .............................................................................. 150
13.3.Security Options ............................................................................................. 150
13.4.Determining the Device Part Number at Run Time ........................................ 152
13.5.Flash Write and Erase Guidelines .................................................................. 153
13.5.1.VDD Maintenance and the VDD Monitor ............................................... 153
13.5.2.PSWE Maintenance ............................................................................... 154
13.5.3.System Clock ......................................................................................... 154
13.6.Minimizing Flash Read Current ...................................................................... 155
14. Power Management.............................................................................................. 159
14.1.Normal Mode .................................................................................................. 160
14.2.Idle Mode........................................................................................................ 161
14.3.Stop Mode ...................................................................................................... 161
14.4.Suspend Mode ............................................................................................... 162
14.5.Sleep Mode .................................................................................................... 162
14.6.Configuring Wakeup Sources......................................................................... 163
14.7.Determining the Event that Caused the Last Wakeup.................................... 164
14.8.Power Management Specifications ................................................................ 166
15. Cyclic Redundancy Check Unit (CRC0) ............................................................. 167
15.1.16-bit CRC Algorithm...................................................................................... 167
15.2.32-bit CRC Algorithm...................................................................................... 169
15.3.Preparing for a CRC Calculation .................................................................... 170
15.4.Performing a CRC Calculation ....................................................................... 170
15.5.Accessing the CRC0 Result ........................................................................... 170
15.6.CRC0 Bit Reverse Feature............................................................................. 174
16. On-Chip DC-DC Converter (DC0) ........................................................................ 175
16.1.Startup Behavior............................................................................................. 176
16.2.High Power Applications ............................................................................. 177
16.3.Pulse Skipping Mode...................................................................................... 177
16.4.Enabling the DC-DC Converter ...................................................................... 178
16.5.Minimizing Power Supply Noise ..................................................................... 179
16.6.Selecting the Optimum Switch Size................................................................ 179
16.7.DC-DC Converter Clocking Options ............................................................... 179
16.8.DC-DC Converter Behavior in Sleep Mode .................................................... 180
16.9.DC-DC Converter Register Descriptions ........................................................ 181
16.10.DC-DC Converter Specifications .................................................................. 182
17. Voltage Regulator (VREG0) ................................................................................. 183
17.1.Voltage Regulator Electrical Specifications .................................................... 183
18. Reset Sources....................................................................................................... 184
18.1.Power-On (VBAT Supply Monitor) Reset ....................................................... 185
18.2.Power-Fail (VDD/DC+ Supply Monitor) Reset................................................ 186
18.3.External Reset ................................................................................................ 188
18.4.Missing Clock Detector Reset ........................................................................ 188
18.5.Comparator0 Reset ........................................................................................ 188
18.6.PCA Watchdog Timer Reset .......................................................................... 188
Rev. 1.4
5
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ C8051F921.PDF Datasheet ] | |
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