|
|
PDF HD6475328CG Data sheet ( Hoja de datos )
| Número de pieza | HD6475328CG | |
| Descripción | Manual Gives a Hardware Description | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HD6475328CG (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
H8/532 Hardware Manual
1 page  
4.8.1 Instructions that Disable Interrupts ···········································································92
4.8.2 Disabling of Exceptions Immediately after a Reset ··················································93
4.8.3 Disabling of Interrupts after a Data Transfer Cycle ··················································93
4.9 Stack Status after Completion of Exception Handling ························································94
4.9.1 PC Value Pushed on Stack for Trace,
Interrupts, Trap Instructions, and Zero Divide Exceptions ·······································96
4.9.2 PC Value Pushed on Stack for Address Error and Invalid
Instruction Exceptions ······························································································96
4.10 Notes on Use of the Stack ····································································································96
Section 5 Interrupt Controller
5.1 Overview ······························································································································97
5.1.1 Features ·····················································································································97
5.1.2 Block Diagram ··········································································································98
5.1.3 Register Configuration ······························································································99
5.2 Interrupt Types ·····················································································································99
5.2.1 External Interrupts ····································································································99
5.2.2 Internal Interrupts ····································································································101
5.2.3 Interrupt Vector Table ·····························································································101
5.3 Register Descriptions ·········································································································103
5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD) ···············································103
5.3.2 Timing of Priority Setting ·······················································································104
5.4 Interrupt Handling Sequence ·····························································································104
5.4.1 Interrupt Handling Flow ··························································································104
5.4.2 Stack Status after Interrupt Handling Sequence ·····················································107
5.4.3 Timing of Interrupt Exception-Handling Sequence ················································108
5.5 Interrupts During Operation of the Data Transfer Controller ············································108
5.6 Interrupt Response Time ····································································································111
Section 6 Data Transfer Controller
6.1 Overview ····························································································································113
6.1.1 Features ···················································································································113
6.1.2 Block Diagram ········································································································113
6.1.3 Register Configuration ····························································································114
6.2 Register Descriptions ·········································································································115
6.2.1 Data Transfer Mode Register (DTMR) ···································································115
6.2.2 Data Transfer Source Address Register (DTSR) ····················································116
6.2.3 Data Transfer Destination Register (DTDR) ·························································116
6.2.4 Data Transfer Count Register (DTCR) ···································································116
6.2.5 Data Transfer Enable Registers A to D (DTEA to DTED) ·····································117
6.3 Data Transfer Operation ·····································································································118
5 Page 
18.3 Software Standby Mode ·····································································································308
18.3.1 Transition to Software Standby Mode ····································································308
18.3.2 Software Standby Control Register (SBYCR) ························································309
18.3.3 Exit from Software Standby Mode ·········································································310
18.3.4 Sample Application of Software Standby Mode ····················································310
18.3.5 Application Notes ···································································································311
18.4 Hardware Standby Mode ····································································································312
18.4.1 Transition to Hardware Standby Mode ···································································312
18.4.2 Recovery from Hardware Standby Mode ·······························································312
18.4.3 Timing Sequence of Hardware Standby Mode ·······················································313
Section 19 E Clock Interface
19.1 Overview ····························································································································315
Section 20 Electrical Specifications
20.1 Absolute Maximum Ratings ······························································································319
20.2 Electrical Characteristics ····································································································319
20.2.1 DC Characteristics ··································································································319
20.2.2 AC Characteristics ··································································································322
20.2.3 A/D Converter Characteristics ················································································326
20.3 MCU Operatinal Timing ····································································································326
20.3.1 Bus Timing ··············································································································327
20.3.2 Control Signal Timing ····························································································330
20.3.3 Clock Timing ··········································································································331
20.3.4 I/O Port Timing ·······································································································333
20.3.5 16-Bit Free-Running Timer Timing ········································································334
20.3.6 8-Bit Timer Timing ·································································································335
20.3.7 Pulse Width Modulation Timer Timing ··································································336
20.3.8 Serial Communication Interface Timing ·································································336
Appendix A Instructions
A.1 Instruction Set ····················································································································337
A.2 Instruction Codes ···············································································································342
A.3 Operation Code Map ··········································································································353
A.4 Instruction Execution Cycles ·····························································································358
A.4.1 Calculation of Instruction Execution States ····························································358
A.4.2 Tables of Instruction Execution Cycles ··································································359
Appendix B Register Field
B.1 Register Addresses and Bit Names ····················································································367
B.2 Register Descriptions ·········································································································372
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD6475328CG.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HD6475328CG | Manual Gives a Hardware Description | Hitachi Semiconductor |
| HD6475328CG | Manual Gives a Hardware Description | Hitachi Semiconductor |
| HD6475328CP | Manual Gives a Hardware Description | Hitachi Semiconductor |
| HD6475328CP | Manual Gives a Hardware Description | Hitachi Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |