|
|
PDF HD6435348SCP Data sheet ( Hoja de datos )
| Número de pieza | HD6435348SCP | |
| Descripción | Single-Chip Microcomputer | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HD6435348SCP (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
OMC 932723248
Hitachi Single-Chip Microcomputer
H8/534, H8/536
HD6475348R, HD6435348R
HD6475368R, HD6435368R
HD6475348S, HD6435348S
HD6475368S, HD6435368S
Hardware Manual
ADE-602-038B
1 page  
4.8.2 Disabling of Exceptions Immediately after a Reset ··················································92
4.8.3 Disabling of Interrupts after a Data Transfer Cycle ··················································92
4.9 Stack Status after Completion of Exception Handling ························································93
4.9.1 PC Value Pushed on Stack for Trace,
Interrupts, Trap Instructions, and Zero Divide Exceptions ·······································95
4.9.2 PC Value Pushed on Stack for Address Error and Invalid
Instruction Exceptions ······························································································95
4.10 Notes on Use of the Stack ····································································································95
Section 5 Interrupt Controller
5.1 Overview ······························································································································97
5.1.1 Features ·····················································································································97
5.1.2 Block Diagram ··········································································································98
5.1.3 Register Configuration ······························································································99
5.2 Interrupt Types ·····················································································································99
5.2.1 External Interrupts ····································································································99
5.2.2 Internal Interrupts ····································································································101
5.2.3 Interrupt Vector Table ·····························································································102
5.3 Register Descriptions ·········································································································104
5.3.1 Interrupt Priority Registers A to F (IPRA to IPRF) ················································104
5.3.2 Timing of Priority Setting ·······················································································105
5.4 Interrupt Handling Sequence ·····························································································105
5.4.1 Interrupt Handling Flow ·························································································105
5.4.2 Stack Status after Interrupt Handling Sequence ·····················································108
5.4.3 Timing of Interrupt Exception-Handling Sequence ················································109
5.5 Interrupts During Operation of the Data Transfer Controller ············································109
5.6 Interrupt Response Time ····································································································112
Section 6 Data Transfer Controller
6.1 Overview ····························································································································113
6.1.1 Features ···················································································································113
6.1.2 Block Diagram ········································································································113
6.1.3 Register Configuration ····························································································114
6.2 Register Descriptions ·········································································································115
6.2.1 Data Transfer Mode Register (DTMR) ···································································115
6.2.2 Data Transfer Source Address Register (DTSR) ····················································116
6.2.3 Data Transfer Destination Register (DTDR) ·························································116
6.2.4 Data Transfer Count Register (DTCR) ···································································116
6.2.5 Data Transfer Enable Registers A to F (DTEA to DTEF) ······································117
6.3 Data Transfer Operation ·····································································································118
6.3.1 Data Transfer Cycle ································································································118
5 Page 
17.7 Handling of Windowed Packages ······················································································319
Section 18 Power-Down State
18.1 Overview ····························································································································321
18.2 Sleep Mode ························································································································322
18.2.1 Transition to Sleep Mode ························································································322
18.2.2 Exit from Sleep Mode ·····························································································322
18.3 Software Standby Mode ·····································································································322
18.3.1 Transition to Software Standby Mode ····································································322
18.3.2 Software Standby Control Register (SBYCR) ························································323
18.3.3 Exit from Software Standby Mode ·········································································324
18.3.4 Sample Application of Software Standby Mode ····················································324
18.3.5 Application Notes ···································································································325
18.4 Hardware Standby Mode ···································································································325
18.4.1 Transition to Hardware Standby Mode ···································································325
18.4.2 Recovery from Hardware Standby Mode ·······························································326
18.4.3 Timing Sequence of Hardware Standby Mode ·······················································326
Section 19 E Clock Interface
19.1 Overview ····························································································································327
Section 20 Electrical Specifications
20.1 Absolute Maximum Ratings ······························································································331
20.2 Electrical Characteristics ····································································································331
20.2.1 DC Characteristics ··································································································331
20.2.2 AC Characteristics ··································································································340
20.2.3 A/D Converter Characteristics ················································································349
20.3 MCU Operational Timing ··································································································350
20.3.1 Bus Timing ··············································································································351
20.3.2 Control Signal Timing ····························································································354
20.3.3 Clock Timing ··········································································································355
20.3.4 I/O Port Timing ·······································································································357
20.3.5 16-Bit Free-Running Timer Timing ········································································358
20.3.6 8-Bit Timer Timing ·································································································359
20.3.7 Pulse Width Modulation Timer Timing ··································································360
20.3.8 Serial Communication Interface Timing ·································································360
20.3.9 A/D Trigger Signal Input Timing ···········································································361
Appendix A Instructions
A.1 Instruction Set ····················································································································363
A.2 Instruction Codes ···············································································································368
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD6435348SCP.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HD6435348SCP | Single-Chip Microcomputer | Hitachi Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |