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PDF FM24C08 Data sheet ( Hoja de datos )
| Número de pieza | FM24C08 | |
| Descripción | 2-Wire Serial EEPROM | |
| Fabricantes | Fudan | |
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FM24C02/04(1)/08(2)/16
2-Wire Serial EEPROM
Data Sheet
May. 2008
Note: 1. FM24C04 not recommend for new design,
please refer to FM24C04A datasheet..
2. FM24C08 not recommend for new design
please refer to FM24C08A datasheet..
FM24C02/04/08/16 2-wrie Serial EEPROM
Version 3.1
Data Sheet
1
1 page  
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to
positive edge clock data into each EEPROM device
and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional
for serial data transfer. This pin is open-drain driven
and may be wire-ORed with any number of other
open-drain or open-collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2,
A1 and A0 pins are device address inputs that are
hard wired for the FM24C02. As many as eight 2K
devices may be addressed on a single bus system
(device addressing is discussed in detail under the
Device Addressing section).
The FM24C04 uses the A2 input for hardwire
addressing and a total of two 4K devices may be
addressed on a single bus system. The A0 and A1
pins are no connects.
The FM24C08 only uses the A2 input for hardwire
addressing and a total of two 8K devices may be
addressed on a single bus system. The A0 and A1
pins are no connects.
The FM24C16 does not use the device address
pins, which limits the number of devices on a
single bus to one. The A0, A1 and A2 pins are no
connects.
WRITE PROTECT (WP): The FM24C02/04/08/16 has
a Write Protect pin that provides hardware data
protection. The Write Protect pin allows normal
read/write operations when connected to ground
(GND). When the Write Protect pin is connected to
VCC, the write protection feature is enabled.
Write Protect Description
WP Pin
Status
WP=VCC
WP=GND
FM24C02
Full (2K) Array
Part of the Array Protected
FM 24C04
FM 24C08
Full (4K) Array
Full (8K) Array
Normal Read/Write Operations
FM 24C16
Upper Half (8K) Array
Memory Organization
FM24C02, 2K SERIAL EEPROM: Internally organized
with 32 pages of 8 bytes each, the 2K requires an
8-bit data word address for random word
addressing.
FM24C04, 4K SERIAL EEPROM: Internally organized
with 32 pages of 16 bytes each, the 4K requires a
9-bit data word address for random word
addressing.
FM24C08, 8K SERIAL EEPROM: Internally organized
with 64 pages of 16 bytes each, the 8K requires a
10-bit data word address for random word
addressing.
FM24C16, 16K SERIAL EEPROM: Internally organized
with 128 pages of 16 bytes each, the 16K requires
an 11-bit data word address for random word
addressing.
FM24C02/04/08/16 2-wrie Serial EEPROM
Version 3.1
Data Sheet
5
5 Page 
Write Operations
Read Operations
BYTE WRITE: A write operation requires an 8-bit
data word address following the device address
word and acknowledgment. Upon receipt of this
address, the EEPROM will again respond with a
zero and then clock in the first 8-bit data word.
Following receipt of the 8-bit data word, the
EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate
the write sequence with a stop condition. At this
time the EEPROM enters an internally timed write
cycle, tWR, to the nonvolatile memory. All inputs are
disabled during this write cycle and the EEPROM
will not respond until the write is complete (refer to
Figure 8).
PAGE WRITE: The 2K EEPROM is capable of an
8-byte page write, and the 4K, 8K and 16K devices
are capable of 16-byte page writes.
A page write is initiated the same as a byte write,
but the microcontroller does not send a stop
condition after the first data word is clocked in.
Instead, after the EEPROM acknowledges receipt
of the first data word, the microcontroller can
transmit up to seven (2K) or fifteen (4K, 8K, 16K)
more data words. The EEPROM will respond with
a zero after each data word received. The
microcontroller must terminate the page write
sequence with a stop condition (refer to Figure 9).
The data word address lower three (2K) or four (4K,
8K, 16K) bits are internally incremented following
the receipt of each data word. The higher data word
address bits are not incremented, retaining the
memory page row location. When the word address,
internally generated, reaches the page boundary,
the following byte is placed at the beginning of the
same page. If more than eight (2K) or sixteen (4K,
8K, 16K) data words are transmitted to the EEPROM,
the data word address will “roll over” and previous
data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally
timed write cycle has started and the EEPROM
inputs are disabled, acknowledge polling can be
initiated. This involves sending a start condition
followed by the device address word. The
read/write bit is representative of the operation
desired. Only if the internal write cycle has
completed will the EEPROM respond with a zero
allowing the read or write sequence to continue.
Read operations are initiated the same way as write
operations with the exception that the read/write
select bit in the device address word is set to one.
There are three read operations: current address
read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data
word address counter maintains the last address
accessed during the last read or write operation,
incremented by one. This address stays valid
between operations as long as the chip power is
maintained. The address “roll over” during read is
from the last byte of the last memory page to the
first byte of the first page. The address “roll over”
during write is from the last byte of the current
page to the first byte of the same page.
Once the device address with the read/write select
bit set to one is clocked in and acknowledged by
the EEPROM, the current address data word is
serially clocked out. The microcontroller does not
respond with an input zero but does generate a
following stop condition (refer to Figure 10).
RANDOM READ: A random read requires a “dummy”
byte write sequence to load in the data word
address. Once the device address word and data
word address are clocked in and acknowledged by
the EEPROM, the microcontroller must generate
another start condition. The microcontroller now
initiates a current address read by sending a
device address with the read/write select bit high.
The EEPROM acknowledges the device address
and serially clocks out the data word. The
microcontroller does not respond with a zero but
does generate a following stop condition (refer to
Figure 11).
SEQUENTIAL READ: Sequential reads are
initiated by either a current address read or a
random address read. After the microcontroller
receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data
word address and serially clock out sequential data
words. When the memory address limit (2K、8K、
16K) is reached, the data word address will “roll
over” and the sequential read will continue. The
sequential read operation is terminated when the
microcontroller does not respond with a zero but
does generate a following stop condition (refer to
Figure 12).
FM24C02/04/08/16 2-wrie Serial EEPROM
Version 3.1
Data Sheet
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet FM24C08.PDF ] | |
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