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PDF HD404889H Data sheet ( Hoja de datos )
| Número de pieza | HD404889H | |
| Descripción | Low-Voltage AS Microcomputers with On-Chip LCD Circuit | |
| Fabricantes | ETC | |
| Logotipo |  |
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HD404849 Series
4-Bit Single-Chip Microcomputer
Rev. 6.0
Sept. 1998
Description
The HD404849 series of HMCS400-series microcomputers is designed to increase program productivity
and also incorporate large-capacity memory. Each microcomputer has an LCD controller/driver, A/D
converter, input capture circuit, 32-kHz oscillator for clock use, and four low-power dissipation modes.
The HD404849 series includes the HD404848 with an 8-kword on-chip ROM, the HD4048412 with a 12-
kword on-chip ROM, the HD404849 with a 16-kword on-chip ROM, and the HD4074849 with a 16-kword
on-chip PROM.
On-chip ROM is available in a PROM (ZTAT™ microcomputer) version and a mask ROM version. A
program can be written to the PROM by a PROM writer, which can dramatically shorten system
development periods and smooth the process from debugging to mass production. PROM programming
specifications are the same as for the 27256.
ZTAT™: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
• 35 I/O pins, including nine high-current pins (15 mA, max.), eight pins multiplexed with LCD segment
pins, and four pins multiplexed with analog input pins
• Four timer/counters
• Eight-bit input capture circuit
• Three timer outputs (including two PWM outputs)
• Two event counter inputs (including one in which the detection edge is programmable)
• Clock-synchronous 8-bit serial interface
• A/D converter (8 channels × 8 bits)
Operation voltage 2.7 V to 6.0 V
• LCD driver (32 segments × 4 commons)
• Built-in oscillators
Main clock: Can be driven by ceramic oscillator, crystal oscillator, or external clock.
Subclock: 32.768-kHz crystal
• Ten interrupt sources
Four by external sources, including two in which the detection edge is programmable
1 page  
HD404849 Series
Item
LCD
Symbol
V1, V2, V3
A/D converter
COM1–
COM4
SEG13–
SEG44
AVCC
AVSS
AN0–AN7
Pin Number
FP-80A, TFP-80C FP-80B
70–72
72–74
66–69
68–71
I/O Function
Power pins for LCD driver. The LCD
power supply division resistors can be
connected and disconnected as
controlled by software.
Voltage conditions are:
VCC ≥ V1 ≥ V2 ≥ V3 ≥ GND
O Common signal pins for LCD
34–65
36–67
O Segment signal pins for LCD
74
3
75–80, 1, 2
76
5
77–80, 1–4 I
Power pin for A/D converter: Connect
it to the same potential as VCC, as
physically close to the VCC pin as
possible
Ground for AVCC: Connect it to the
same potential as GND, as physically
close to the GND pin as possible
Analog input pins for A/D converter
5
5 Page 
HD404849 Series
Bits in the interrupt control bits area and register flag area can be set and reset by the
SEM/SEMD and REM/REMD instructions, and tested with the TM/TMD instructions.
Other instructions have no effect on these bits. Note the following restrictions for each
bit.
IE
IM
LSON
IAOF
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
DTON
Not used
SEM/SEMD
Allowed
Not executed
Not executed
Allowed
Allowed
Not executed in active mode
Used in subactive mode
Not executed
REM/REMD
Allowed
Allowed
Allowed
Not executed
Inhibited
Allowed
Not executed
TM/TMD
Allowed
Allowed
Inhibited
Inhibited
Allowed
Allowed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST cannot be guaranteed.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
11
11 Page | ||
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| PDF Descargar | [ Datasheet HD404889H.PDF ] | |
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