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74C08 fiches techniques PDF

Fairchild - Quad 2-Input AND Gate

Numéro de référence 74C08
Description Quad 2-Input AND Gate
Fabricant Fairchild 
Logo Fairchild 





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74C08 fiche technique
October 1987
Revised May 2002
MM74C08
Quad 2-Input AND Gate
General Description
The M M74C08 e mploys c omplementary MOS (CMOS)
transistors to ac hieve wide power supply operating range,
low po wer co nsumption an d hi gh no ise ma rgin, the se
gates provide basic functions used in the implementation of
digital inte grated cir cuit syste ms. T he N- an d P -channel
enhancement mode tr ansistors p rovide a s ymmetrical c ir-
cuit with output swing essentially equal to the supply volt-
age. N o D C po wer oth er tha n t hat caused by l eakage
current is consumed during s tatic c ondition. A ll i nputs ar e
protected from da mage due to static di scharge b y di ode
clamps to VCC and GND.
Features
s Wide supply voltage range: 3.0V to 15V
s Guaranteed noise margin: 1.0V
s High noise immunity: 0.45 VCC (typ.)
s Low power TTL compatibility:
Fan out of 2 driving 74L
s Low power consumption: 10 nW/package (typ.)
Ordering Code:
Order Number Package Number
Package Description
MM74C08M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74CD8N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
H = HIGH Level
L = LOW Level
A
L
L
H
H
Inputs
B
L
H
L
H
Outputs
Y
L
L
L
H
Top View
© 2002 Fairchild Semiconductor Corporation DS005878
www.fairchildsemi.com
http://www.Datasheet4U.com

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