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PDF HD404316S Data sheet ( Hoja de datos )
| Número de pieza | HD404316S | |
| Descripción | 4-bit HMCS400-series microcomputer | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD404318 Series
Rev. 6.0
Sept. 1998
Description
The HD404318 Series is 4-bit HMCS400-series microcomputer with large-capacity memory designed to
increase program productivity. Each microcomputer has an A/D converter and input capture timer built in.
They also come with high-voltage I/O pins that can directly drive a fluorescent display.
The HD404318 Series includes four chips: the HD404318 with 8-kword ROM; the HD404316 with 6-
kword ROM; the HD404314 with 4-kword ROM; the HD4074318 with 8-kword PROM.
The HD4074318 is a PROM version ZTAT™ microcomputer. Programs can be written to the PROM by a
PROM writer, which can dramatically shorten system development periods and smooth the process from
debugging to mass production. (The PROM program specifications are the same as for the 27256.)
ZTAT™: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
• 34 I/O pins
One input-only pin
33 input/output pins: 21 pins are high-voltage pins (40 V, max.)
• On-chip A/D converter (8-bit × 8-channel)
• Three timers
One event counter input
One timer output
One input capture timer
• 8-bit clock-synchronous serial interface (1 channel)
• Alarm output
• Built-in oscillators
Ceramic or crystal oscillator
External clock drive is also possible
1 page  
HD404318 Series
Pin Description in PROM Mode
The HD4074318 is a PROM version of a ZTAT™ microcomputer. In PROM mode, the MCU stops
operating, thus allowing the user to program the on-chip PROM.
Pin Number
DP-42S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
FP-44A
39
40
41
42
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
24
25
26
MCU Mode
Pin
RA 1/V disp
R00/SCK
R01/SI
R02/SO
R03/TOC
TEST
RESET
OSC1
OSC2
GND
AVSS
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
R41/AN5
R42/AN6
R43/AN7
AVCC
VCC
D0/INT0
D1/INT1
D2/EVNB
D3/BUZZ
D4/STOPC
D5
D6
D7
D8
I/O
I
I/O
I/O
I/O
I/O
I
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PROM Mode
Pin
I/O
VCC
VCC
VPP
RESET
VCC
GND
GND
O0
O1
O2
O3
O4
O5
O6
O7
VCC
VCC
M0
M1
A1
A2
A3
A4
A9
VCC
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
5
5 Page 
HD404318 Series
Note:
SEM/SEMD
REM/REMD
TM/TMD
IE
IM
Allowed
Allowed
Allowed
IAOF
IF
ICSF
ICEF
Not executed
Allowed
Allowed
RAME
RSP
Not executed
Allowed
Inhibited
WDON
Allowed
Not executed
Inhibited
ADSF
Allowed
Inhibited
Allowed
Not used
Not executed
Not executed
Inhibited
WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD
instruction must not be executed for ADSF during A/D conversion. If the TM or TMD instruction is
executed for the inhibited bits or non-existing bits, the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
Memory registers
$040 MR(0)
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)
MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)
$3C0
$3FF
Stack area
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
PC13–PC0 : Program counter
ST: Status flag
CA: Carry flag
Bit 3
$3FC ST
$3FD PC10
$3FE CA
$3FF PC3
Bit 2
PC13
PC9
PC6
PC2
Bit 1
PC12
PC8
PC5
PC1
Bit 0
PC11
PC7
PC4
PC0
Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position
11
11 Page | ||
| Páginas | Total 66 Páginas | |
| PDF Descargar | [ Datasheet HD404316S.PDF ] | |
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