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PDF AD8193 Data sheet ( Hoja de datos )
| Número de pieza | AD8193 | |
| Descripción | Buffered 2:1 TMDS Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8193 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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FEATURES
2 inputs, 1 output HDMI/DVI high speed signal switch
Pin-to-pin compatible with the AD8194
Enables HDMI 1.3-compliant receiver
4 TMDS channels per input/output
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Fully buffered unidirectional inputs/outputs
Supports more than 20 m of input cable at 1080i, more
than 10 m of input cable at 1080p, and more than 6
meters of input cable at 1080p, 12-bit color
Matched 50 Ω input and output on-chip terminations
Low added jitter
Single-supply operation (3.3 V)
Standards compliant: HDMI receiver, DVI
32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP
APPLICATIONS
Advanced television (HDTV) sets
Multiple input displays
Projectors
A/V receivers
Set-top boxes
GENERAL DESCRIPTION
The AD8193 is a low cost quad 2:1 TMDS® switch for high
speed HDMI™/DVI video applications. Its primary function is
to switch the high speed signals from one of two single-link
(HDMI or DVI) sources to the single-link output. The AD8193
is a fully buffered switch solution with 50 Ω input and output
terminations, providing full-swing output signal recovery and
minimizing reflections for improved system signal integrity.
The AD8193 is provided in a space-saving, 32-lead, LFCSP,
surface-mount, RoHS-compliant, plastic package and is specified
to operate over the −40°C to +85°C temperature range.
Buffered 2:1 TMDS Switch
AD8193
FUNCTIONAL BLOCK DIAGRAM
AVCC AVEE
S_SEL
VTTI
CONTROL
LOGIC
AD8193
IP_A[3:0]
IN_A[3:0]
+
–
IP_B[3:0]
IN_B[3:0]
+
–
VTTI
4
4
Rx
4
4
SWITCH
CORE
4
Tx 4
HIGH SPEED
BUFFERED
VTTO
+ OP[3:0]
– ON[3:0]
Figure 1.
TYPICAL APPLICATION
HDTV SET
HDMI
RECEIVER
SET-TOP BOX
AD8193
DVD PLAYER
Figure 2. Typical AD8193 Application for HDTV Sets
PRODUCT HIGHLIGHTS
1. Data supports rates up to 2.25 Gbps, enabling greater than
1080p deep color (12-bit color) HDMI formats and greater
than UXGA (1600 × 2300) DVI resolutions.
2. Fully buffered unidirectional inputs and outputs.
3. Supports more than 20 meters of a typical 24 AWG input
cable at 1080i, more than 10 meters at 1080p, and more
than 6 meters at 1080p, 12-bit color.
4. Matched 50 Ω on-chip input and output terminations
improve system signal integrity.
5. Single-pin source select bit.
6. Input terminations are automatically switched out for the
unselected input.
7. Low added jitter.
Rev. 0
Information furnished by Analog D evices is believed to b e accurate and reliable. However, no
responsibliity isassumed byAnalogDevices for its use,nor for any infringementsofpatentsorother
rightsof third partiesthat mayresultfrom its use.Specifications subjectto change withoutnotice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksaretheproperty oftheir respective owners.
One T echnology Way, P .O. B ox 91 06, Nor wood, MA 020 62-9106, U. S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
http://www.Datasheet4U.com
1 page  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN_A2
IP_A2
VTTI
IN_A3
IP_A3
AVCC
OP3
ON3
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
AD8193
TOP VIEW
(Not to Scale)
24 IP_B2
23 IN_B2
22 AVCC
21 IP_B1
20 IN_B1
19 VTTI
18 IP_B0
17 IN_B0
AD8193
NOTES
1. THE AD8193 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE
OF THE PACKAGE, WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE TO MEET
THERMAL SPECIFICATIONS.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1 IN_A2
2 IP_A2
3, 19 VTTI
4 IN_A3
5 IP_A3
6, 22 AVCC
7 OP3
8 ON3
9 OP2
10 ON2
11, 27, ePAD
AVEE
12 OP1
13 ON1
14 VTTO
15 OP0
16 ON0
17 IN_B0
18 IP_B0
20 IN_B1
21 IP_B1
23 IN_B2
24 IP_B2
25 IN_B3
26 IP_B3
28 IN_A0
29 IP_A0
30 S_SEL
31 IN_A1
32 IP_A1
Type 1
HS I
HS I
Power
HS I
HS I
Power
HS O
HS O
HS O
HS O
Power
HS O
HS O
Power
HS O
HS O
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
HS I
Control
HS I
HS I
Description
High Speed Input Complement.
High Speed Input.
Input Termination Supply. Nominally connected to AVCC.
High Speed Input Complement.
High Speed Input.
Positive Power Supply. 3.3 V nominal.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
Negative Power Supply. 0 V nominal.
High Speed Output.
High Speed Output Complement.
Output Termination Supply. Nominally connected to AVCC.
High Speed Output.
High Speed Output Complement.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Source Selector Pin.
High Speed Input Complement.
High Speed Input.
1 HS = high speed, I = input, O = output.
Rev. 0 | Page 5 of 16
5 Page 
AD8193
APPLICATION NOTES
SWITCHING HIGH SPEED SIGNALS
The AD8193 is a quad 2:1 TMDS switch that is used to switch
the high speed signals of two input HDMI links to a single
HDMI output.
SWITCHING LOW SPEED SIGNALS
Because the AD8193 is a TMDS-only switch, a complete HDMI
switch solution requires another component to switch the low
speed DDC channels.
The HDMI 1.3 specification places a number of restrictions on
the low speed signal path that limit the selection of a suitable
low cost DDC switch. The first requirement is that the switch
must be bidirectional to convey the I2C® protocol signals that
pass through it. A CMOS device is the simplest switch with this
capability.
The second HDMI requirement for the DDC signals is that the
total DDC signal path capacitance be less than 50 pF. The total
capacitance comprises the HDMI connector, the PC board
traces, the DDC switch, and the input capacitance of the HDMI
receiver. As a practical design consideration, a suitable DDC
switch has a total channel capacitance of less than 10 pF.
Finally, the channel on resistance (RON) of the DDC switch must
not be too high, otherwise the voltage drop across it violates the
maximum VOL of the I2C signals. Any switch with an on resistance
of approximately 100 Ω is sufficient in a typical application, assum-
ing that the end application includes an I2C-compliant receiver
device. Switches with lower channel on resistance have improved
VOL performance.
For the AD8193 evaluation board, the MC74LVX4053 was
chosen to switch the low speed signals. This part has a maximum
RON of 108 Ω and a maximum parasitic capacitance of 10 pF.
Refer to the Evaluation Board section for details on how to use
the MC74LVX4053 with the AD8193 in an application.
PCB LAYOUT GUIDELINES
The AD8193 is used to switch HDMI/DVI video signals, which
are differential, unidirectional, and high speed (up to 2.25 Gbps).
The channels that carry the video data must be controlled
impedance, terminated at the receiver, and capable of operating
up to at least 2.25 Gbps. It is especially important to note that
the differential traces that carry the TMDS signals should be
designed with a controlled differential impedance of 100 Ω.
The AD8193 provides single-ended 50 Ω terminations on chip
for both its inputs and outputs. Transmitter termination is not
fully specified by the HDMI standard, but the inclusion of the
50 Ω output terminations improves the overall system signal
integrity.
TMDS Signals
The audiovisual (AV) data carried on these high speed channels
is encoded by a technique called Transition Minimized Differential
Signaling (TMDS) and, in the case of HDMI, is also encrypted
according to the high bandwidth digital content protection
(HDCP) standard.
In the HDMI/DVI standard, four differential pairs carry the
TMDS signals. For DVI, three of these pairs are dedicated to
carrying RGB video and sync data. For HDMI, audio data is
also interleaved with the video data; the DVI standard does
not incorporate audio information. The fourth high speed
differential pair is used for the AV data-word clock and runs
at one-tenth the speed of the TMDS data channels.
The four high speed channels of the AD8193 are identical.
No concession was made to lower the bandwidth of the fourth
channel for the pixel clock, so any channel can be used for any
TMDS signal. The user chooses which signal is routed over which
channel. Additionally, the TMDS channels are symmetrical; there-
fore, the p and n of a given differential pair are interchangeable,
provided the inversion is consistent across all inputs and outputs of
the AD8193. However, the routing between inputs and outputs
through the AD8193 is fixed. For example, Output Channel 0
always switches between Input A0 and Input B0, and so forth.
The AD8193 buffers the TMDS signals, and the input traces can
be considered electrically independent of the output traces. In
most applications, the quality of the signal on the input TMDS
traces is more sensitive to the PCB layout. Regardless of the data
being carried on a specific TMDS channel, or whether the
TMDS line is at the input or the output of the AD8193, all four
high speed signals should be routed on a PCB in accordance
with the same RF layout guidelines.
Layout for the TMDS Signals
The TMDS differential pairs can be either microstrip traces,
routed on the outer layer of a board, or stripline traces, routed
on an internal layer of the board. If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stackup. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 Ω. The
characteristic impedance of a differential pair is a function of
several variables, including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PC board binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path; therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. Additionally, to prevent
unwanted signal coupling and interference, route the TMDS
signals away from other signals and noise sources on the PCB.
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD8193.PDF ] | |
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