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PDF KLMCG8GE4A-A001 Data sheet ( Hoja de datos )
| Número de pieza | KLMCG8GE4A-A001 | |
| Descripción | e-MMC | |
| Fabricantes | Samsung | |
| Logotipo |  |
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Rev. 1.1, Dec 2011
KLMxGxGE4A-A001
Samsung e·MMC Product family
e.MMC 4.41 Specification compatibility
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2011 Samsung Electronics Co., Ltd. All rights reserved.
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http://www.Datasheet4U.com
1 page  
KLMxGxGE4A-A001
datasheet
Rev. 1.1
e·MMC
INTRODUCTION
The SAMSUNG e·MMC is an embedded MMC solution designed in a BGA package form. e·MMC operation is identical to a MMC card and therefore is a
simple read and write to memory using MMC protocol v4.41 which is a industry standard.
e·MMC consists of NAND flash and a MMC controller. 3V supply voltage is required for the NAND area (VDDF) whereas 1.8V or 3V dual supply voltage
(VDD) is supported for the MMC controller. Maximum MMC interface frequency of 52MHz and maximum bus widths of 8 bit are supported.
There are several advantages of using e·MMC. It is easy to use as the MMC interface allows easy integration with any microprocessor with MMC host.
Any revision or amendment of NAND is invisible to the host as the embedded MMC controller insulates NAND technology from the host. This leads to
faster product development as well as faster times to market.
The embedded flash mangement software or FTL(Flash Transition Layer) of e·MMC manages Wear Leveling, Bad Block Management and ECC. The
FTL supports all features of the Samsung NAND flash and achieves optimal performance.
1.0 PRODUCT LIST
[Table 1] Product List
Capacities e·MMC Part ID NAND Flash Type User Density (%)
16GB KLMAG2GE4A-A001 64Gb MLC x 2
32GB KLMBG4GE4A-A001 64Gb MLC x 4
91.0%
64GB KLMCG8GE4A-A001 64Gb MLC x 8
Power System
Package size
Pin Configuration
- Interface power : VDD
(1.70V ~ 1.95V or
2.7V ~ 3.6V)
- Memory power : VDDF
(2.7V ~ 3.6V)
12mm x 16mm x 1.0mm
12mm x 16mm x 1.2mm
169FBGA
2.0 KEY FEATURES
MultiMediaCard System Specification Ver. 4.41 compatible. Detail description is referenced by JEDEC Standard
SAMSUNG e·MMC supports below special features which are being discussed in JEDEC
- High Priority Interrupt scheme is supported
- Back ground operation is supported.
Full backward compatibility with previous MultiMediaCard system ( 1bit data bus, multi-e·MMC systems)
Data bus width : 1bit (Default) , 4bit and 8bit
MMC I/F Clock Frequency : 0 ~ 52MHz
MMC I/F Boot Frequency : 0 ~ 52MHz
Temperature : Operation(-25C ~ 85C), Storage without operation (-40C ~ 85C)
Power : Interface power → VDD (1.70V ~ 1.95V or 2.7V ~ 3.6V) , Memory power → VDDF(2.7V ~ 3.6V)
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5 Page 
KLMxGxGE4A-A001
datasheet
Rev. 1.1
e·MMC
4.2 Reliable Write
[Table 6] EXT_CSD value for reliable write
Name
Data Reliability Supports
Field
WR_REL_PARAM
Size (Bytes)
1
Cell Type
R
CSD-slice
166
Value
0x05
Reliable write with EN_REL_WR is 0x1 supports atomicity of sector unit.
The block size defined by SET_BLOCKLEN (CMD16) is ignored and reliable write is executed as only 512 byte length. There is no ilmit on the size of the
reliable write.
[Table 7] EXT_CSD value for reliable write
Name
Reliable Write Sector Count
Field
REL_WR_SEC_C
Size
(Bytes)
1
Cell Type
R
CSD-slice
[222]
Value
0x01
4.3 Secure Trim
Secure Trim operation consists of Secure Trim Step1 and Secure Trim Step2.
In Secure Trim Step 1 the host defines the range of write blocks that it would like to mark for the secure purge.
[Table 8] EXT_CSD value for secure trim
Field
Definitions
SEC_TRIM_MULT Secure Trim Step2 Timeout = 300ms x ERASE_TIMEOUT_MULT x SEC_TRIM_MULT
Value
0x11
Area marked by Secure Trim Step1 is shown as EXT_CSD[181](ERASED_MEM_CONT) before Secure Trim Step2 is completed.
When Secure Trim Step2 is issued, if there is no data marked by Secure Trim Step1, Secure Trim Step2 does not work.
4.4 High Priority Interrupt
High Priority Interrupt is to stop ongoing operation and perform read operation with high priority
Command set for High Priority Interrupt operation is the below
[Table 9] Command List for High Priority Interrupt
CMD Index
CMD12
Type
ac
Argument
[31:16] – RCA*
[15:1] – stuff bits
[0] – High Priority Interrupt *
*To be used only to send a High
Priority Interrupt
Resp
R1b
Abbreviation
STOP_TRANSMISSION
Command Description
If High Priority Interrupt flag is set the
device shall interrupt its internal operations
in a well defined timing
Interruptible commands by read while write operation are the below.
[Table 10] List of Interruptible Command
Commands
CMD24
CMD25
Names
WRITE SINGLE BLOCK
WRITE MULTIPLE BLOCKS
CMD25
RELIABLE WRITE
CMD38
CMD6
ERASE
TRIM
SECURE ERASE
SECURE TRIM
SWITCH
Notes
-
-
Stopping a reliable write command
with ‘High Priority Interrupt’ flag set turns that command into a reliable write command
-
-
-
-
BACKGROUND OPERATION ONLY
- 10 -
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