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PDF HCS412 Data sheet ( Hoja de datos )
| Número de pieza | HCS412 | |
| Descripción | Code Hopping Encoder and Transponder | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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HCS412
KEELOQ® Code Hopping Encoder and Transponder
FEATURES
Security
• Programmable 64-bit encoder crypt key
• Two 64-bit IFF keys
• Keys are read protected
• 32-bit bi-directional challenge and response using
one of two possible keys
• 69-bit transmission length
• 32-bit hopping code,
• 37-bit nonencrypted portion
• Programmable 28/32-bit serial number
• 60-bit, read protected seed for secure learning
• Two IFF encryption algorithms
• Delayed counter increment mechanism
• Asynchronous transponder communication
• Transmissions include button Queuing
information
Operating
• 2.0V to 6.3V operation
• Three switch inputs: S2, S1, S0 – seven functions
• Battery-less bi-directional transponder capability
• Selectable baud rate and code word blanking
• Automatic code word completion
• Battery low detector
• PWM or Manchester data encoding
• Combined transmitter, transponder operation
• Anticollision of multiple transponders
• Passive proximity activation
• Device protected against reverse battery
• Intelligent damping for high Q LC-circuits
• 100 mVPP sensitive LC input
Typical Applications
• Automotive remote entry systems
• Automotive alarm systems
• Automotive immobilizers
• Gate and garage openers
• Electronic door locks (Home/Office/Hotel)
• Burglar alarm systems
• Proximity access control
PACKAGE TYPES
PDIP, SOIC
S0 1
S1 2
S2/RFEN/LC1 3
LC0 4
8 VDD
7 LED
6 DATA
5 GND
BLOCK DIAGRAM
VDD Power
Control
Oscillator
Configuration Register
S0
S1
Wake-up
Debounce
Control
Address
Decoding
EEPROM
Logic
and
Queuer
LED
LED
Control
LC0
RFEN/S2/LC1
DATA
DATA
Driver
PPM
Detector
DATA
PPM
Manch.
Encoder
Other
• Simple programming interface
• On-chip tunable RC oscillator, ± 10%
• On-chip EEPROM
• 64-bit user EEPROM in Transponder mode
• Battery-low LED indication
• Serialized Quick Turn Programming (SQTPSM )
• 8-pin PDIP/SOIC
• RF Enable output
• ASK and FSK PLL interface option
• Built in LC input amplifier
© 2011 Microchip Technology Inc.
DS41099D-page 1
http://www.Datasheet4U.com
1 page  
FIGURE 2-4: DATA PIN DIAGRAM
DATA
IN
<
OE >
DOAUTTA>
120 kΩ
DATA
HCS412
FIGURE 2-5: LED PIN DIAGRAM
LED
R
LED_ON >
FIGURE 2-6: TYPICAL APPLICATION CIRCUITS
Battery-less Short Range Transponder
S0
S1
LC1
LC0
1
2
3
4
8 VDD
7 LED
6 DATA
5 GND
Long Range / Proximity Activated Transponder / Encoder
S0
S1
LC1
LC0
1
2
3
4
8 VDD
7 LED
6 DATA
5 GND
RF
Short Range Transponder with RFEN Control / Long Range Encoder
S0
S1
RFEN
LC0
1
2
3
4
8 VDD
7 LED
6 DATA
5 GND
RF
© 2011 Microchip Technology Inc.
DS41099D-page 5
5 Page 
3.2.2 CYCLE REDUNDANCY CHECK (CRC)
The CRC bits may be used to check the received data
integrity, bu t it is no t recommended wh en o perating
near the low voltage trip point, see Note below.
The CRC is calculated on the 65 previously transmitted
bits (Figure 3-2), detecting all single bit and 66% of all
double bit errors.
EQUATION 3-1: CRC CALCULATION
and CRC[]1 n1+ = CRC []0 n ⊕ Din
CRC[]0 n1+
with
= ()CR C[]0 n ⊕ Din ⊕ CRC []1 n
CRC[]1, 0 0 = 0
and Din the nth transmission bit 0 ≤n ≤64
Note: The CRC may be wrong when the operat-
ing voltage is near VLOW trip point. VLOW is
sampled twice each transmission, once for
the CRC calculation (DATA output is LOW)
and once when the VLOW bit is transmitted
(DATA output is HIGH). VDD varying slightly
during a transmission could lead to a differ-
ent VLOW status transmitted than that used
in the CRC calculation.
Work a round: If the CRC is in correct,
recalculate for the opposite value of VLOW.
3.2.3 LOW VOLTAGE DETECTOR STATUS
(VLOW)
The low volt age detector result is included in every
transmitted code word.
The HCS41 2 sa mples the vol tage detector outpu t at
the onset of a transmission and just before the VLOW
bit is transmitted in each code word. The first sample is
used in the CRC calculation and the subsequent sam-
ples determine what VLOW value will be transmitted.
The transmitted VLOW status will be a ‘0’ as long as
VDD remains above the selected low voltage trip point.
VLOW wi ll cha nge to a ‘ 1’ i f V DD drops b elow th e
selected low voltage trip point.
TABLE 3-2: LOW VOLTAGE STATUS BIT
VLOW
0
1
Description
VDD is above trip voltage (VLOWSEL)
VDD is below trip voltage (VLOWSEL)
TABLE 3-3:
LOW VOLTAGE TRIP POINT
SELECTION OPTIONS
Nominal
VLOWSEL Trip
Point
Description
0 2.2V for 3V battery applications
1 4.4V for 6V battery applications
© 2011 Microchip Technology Inc.
HCS412
3.2.4 COUNTER OVERFLOW BITS (OVR1,
OVR0)
The Counter Overflow Bits may be utilized to increase
the synchron ization counter range from th e nomin al
65,535 to 131,070 or 196,605.
The bits must be programmed during production as ‘1’s
to be ut ilized. OVR0 is cleared the f irst time the syn-
chronization counter wrap s from FF FFh to 00 00h.
OVR1 is cleare d the second time the synchronization
counter wraps to zero. The two bits remain at ‘0’ after
all subsequent counter wraps.
3.2.5 EXTENDED SERIAL NUMBER (XSER)
The Exte nded Serial Number o ption d etermines
whether the serial number is 28 or 32 bits.
When configured for a 28-bit serial number, the most
significant nibble of the 32 bits reserved for the serial
number is replaced with a copy of the 4-bit button sta-
tus, Figure 3-2.
3.2.6 DISCRIMINATION VALUE (DISC)
The Discrimin ation Value is a 10-bit fixed val ue typi-
cally used by the d ecoder in a post-decryptio n check.
It may be any value, but in a typical system it will be
programmed as the 10 Least Significant bit s of th e
serial number.
The discrimination bits are part of the information that
form the en crypted portion of the transmissio n
(Figure 3-2). After the receiver has decrypted a trans-
mission, the discrimination bits a re checked a gainst
the receiver’s stored value to verify that the decryption
process was valid. If the discriminatio n value was pro-
grammed equa l to the 10 LSb’ s of th e seria l number
then it may merely be compared to the respective bits
of the received se rial number.
3.2.7 SEED CODE WORD DATA FORMAT
The Seed Code Word transmission allows for what is
known as a secure learning function, increasing a sys-
tem’s security.
The seed code word also consists of 69 bits, but the 32
bits of code hopping data and the 28 bits of fixed data
are replaced b y a 60 -bit see d valu e that wa s sto red
during prod uction (Fi gure 3-4). In stead of using the
normal key g eneration i nputs to create the crypt ke y,
this seed value is used.
Seed transmissions are either:
• permanently enabled
• permanently disabled
• temporarily enabled (limited) until the 7 Least Sig-
nificant bits of the synchronization counter wrap
from 7Fh to 00h.
The Seed Enable (SEED) andTemporary Seed Enable
(TMPSD) configu ration optio ns control th e fun ction
(Table 3-4).
DS41099D-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HCS412.PDF ] | |
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