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PDF ICS31202 Data sheet ( Hoja de datos )
| Número de pieza | ICS31202 | |
| Descripción | Dual Frequency Synthesizer | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS31202 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS31202
Preliminary Product Preview
Dual Frequency Synthesizer
General Description
The ICS31202 is an integrated Dual Frequency Synthesizer
designed for RF Personal Communication systems requiring
two independent frequencies. It is one of the lowest cost and
smallest size solutions for 900MHz applications.
The ICS31202 contains two dual modulus prescalers. A 32/
33 prescaler can be selected for each RF synthesiz.eAr common
reference divider chain is included for required frequency
resolution. Combined with a high quality reference oscillator
and loop filter , the ICS31202 provides the tuning voltages
for the external VCO's to generate very stable, low noise RF
Local Oscillator signals. Serial data is transferred using a
three wire interface. ICS31202 allows synchronous loading
of counters via data line. Crystal inputs are in parallel mode.
The ICS31202 is fabricated using state-of-the art CMOS
process. It is available in a 16-pin 4.4mm TSSOP package
with 0.65mm pitch. The ICS31202 is a direct replacement
for Toshiba TB31202.
Features
Smallest Size Dual RF Sythesizer in the market.
Integrated Dual PLL with prescalers
Dual Modulus Prescaler: 32/33
Provides excellent isolation between Tx, Rx signals.
Input frequency range of 200-600 MHz
2.7V to 4.5V operation
Software controlled Power Down Mode
Selectable charge pump current levels (100 to 800 µA)
Current consumption, 3mA per channel @ 2.7V/500MHz
Synchronous loading of counters
High Input sensitivity, 87-100dBµV (-24dBm)
16-pin TSSOP Package
Applications
900MHz Cordless telephone systems (DCT, ISM, PHS, CT2)
Personal communications systems (GSM, PDC, PCS)
Cellular telephone systems
CATV, Cable Modems
Other RF/wireless communication systems
Block Diagram
FIN1 =
Figure 1
FXIN (32N1 +A1) , D= 4 to 4068, N1 ≤ 4068, A1=0 to 31, Channel Spacing = 2x FXIN
DD
FIN2 = FXIN (32N2 +A2) , D= 4 to 4068, N2 ≤ 4068, A2=0 to 31, Channel Spacing = 2x FXIN
DD
ICS31202 Rev C 05/28/98
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
http://www.Datasheet4U.com
1 page  
ICS31202
Preliminary Product Preview
3.0 Programmable Dividers (CH1, CH2)
CH1 and CH2 are each composed of a 5 bit swallow counter (A), a 12 bit programmable counter (N), and 64/66 Dual
Modulus Prescalers.
The swallow and programmable counters provide division ratios from 2048 to 262,142 in even multiples.
The group code "10" enables CH1 programming. The group code "01" enables CH2 programming.
Ü Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15 Bit16 Bit17 Bit18 Bit19
A0 A1 A2 A3 A4 N0 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
Swallow counter : A
Programmable counter : N
Group Code
CH1 : "10"
CH2 : "01"
4.0 Reference Divider
This block sets the reference frequency of the PLL.
The reference divider is composed of a 12 bit programmable divider and a fixed divide by two divid.er
The reference divider is programmable from 16 to 8192 in even multiples.
Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14
Ü D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 1 1
Reference divider
Group code
5.0 Control Register
The Control Register can be programmed to the following modes of operation:
LSB
ÜT
CH1 CH2
CP CP1 CP2 SB1 CP1 CP2 SB2 SBR LD1 LD2 SW
0
0
Test/ Charge
Low pump
power polarity
T
CH1
Charge
pump
current
CP
CP1, 2
SB1,2
SBR
LD1, 2
SW
CH1 Charge pump
standby output current
Reference Lock
divider detector
standby
Filter
switch
: Bit for test mode
: Toggle bit for charge pump output polarity reversal
: Select bits for charge pump output current
: Standby control bit for CH1, CH2
: Standby control bit for reference divider
: Control bit for lock detector output
: Control bit for filter switch
Group
Code
5
5 Page 
ICS31202
Preliminary Product Preview
7.0 Reference Dat a (Typ.) VDD = 3V, Fin1,Fin2= 500MHz
CH1
NN
NS
SN
SS
SS
CH2
Reference
Divider
On
On
On
On
OFF
Low Power Mode
<9.5
<5.5
<5.5
<700
<10
Unit
mA
mA
mA
µA
µA
N : Normal
S : Standby state
8.0 T est Circuit
Test Circuit shown in Figure 5 is used to generate the characterization plots.
Figure 5
DC/AC Parametric Test Circuit
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ICS31202.PDF ] | |
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