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PDF LD7271 Data sheet ( Hoja de datos )
| Número de pieza | LD7271 | |
| Descripción | Smart Photoflash Capacitor Charger | |
| Fabricantes | Leadtrend | |
| Logotipo |  |
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LD7271
09/13/2011
Smart Photoflash Capacitor Charger with Integrated MOS
REV：02
General Description
The LD7271 is an ide al charge control IC for flash un its,
featuring i nternal s oft st art, adjustable ch arging curre nt
and o utput vol tage. It provid es a charg ing algor ithm to
speed up the charging with higher efficiency. The LD7271
can o perate i n des ired c onstant peak c urrent of ei ght
different levels bet ween 0.6A and 1.3A, b y clocking th e
CHARGE pin.
The LD7271 i s availa ble in a space-savi ng W DFN-8L
2mm x 2mm package and is ideal for DSC flash unit.
g Patented
Features
• 1.8V~6V Battery Voltage Range
• Adjustable Output Voltage
• Adjustable Input Current
• Integrated 47V Power MOS
• False Triggering Prevention
• Soft Start
• Output Voltage Overcharge Protection
• High Efficiency
Applications
• DSC Flash Unit
• Camera Phone
Typical Application
D1/FT01P80
C2
72μF
R1
130kΩ
R2
130kΩ
1μF
C1
10μF~22μF
R3 CS ≤ 1nF*
1kΩ
RP
RN
* If LX pin spike is over 47V, please add CS to reduce spike.
CS ≤ 1nF is recommended.
Fig.1
Leadtrend Technology Corporation
LD7271-DS-02, SEP. 2011
1
www.leadtrend.com.tw
http://www.Datasheet4U.com
1 page  
LD7271
PARAMETER CONDITIONS
DONE#
DONE# Output Low Voltage
DONE# Output High Voltage
IDONE#=1mA
IDONE#=-1mA, VCC-VDONE#
Impedance to GND
Charge Pin to GND
Trigger Pin to GND
OUTP Pin to GND
OUTN Pin to GND
IPEAK Clock hi gh a nd l ow t ime of
Charge Pin
Subsequent Pulses
Total clock pulse setting time of
Charge Pin
Others
Thermal Shutdown
Max ON Time
Propagation Delay
* ILM2-8 are guaranteed by design.
(Trigger=High) delay to
OUTP and OUTN
MIN TYP MAX UNITS
0.1 V
0.1 V
100k
100k
20k
20k
2
Ω
Ω
Ω
Ω
μs
200 μs
150
30
60
°C
μs
ns
Leadtrend Technology Corporation
LD7271-DS-02, SEP. 2011
5
www.leadtrend.com.tw
5 Page 
LD7271
Fig. 14
The signal of IGBT gate will be high according to following
sequence.
1. VCC>UVLO (ON) (typical 2.65V)
2. Charge pin turned to low once and DONE# pin turned
to low once.
3. Trigger pin is high and charge pin is low.
D1/CHBD 4004
C2
90μF
R1
130kΩ/1%
R2
130kΩ/1%
Maximum ON Time
To protect agai nst insufficient current from a poor po wer
source (i e., an almost disch arged b attery) and un able to
reach current limit value in ti me, the LD 7271 will em ploy
maximum on- time function for it. Once ON-time of
charging period exceeds 30μs, the LD7271 will be latched
off in regardless of current limit detection.
Adjust Output Voltage
A resistor divi der can b e con nected to th e center of the
dual dio de to elimin ate the leakag e curr ent af ter the
charging completes. Fig.15 shows the application circuit
of resistor divider.
R3
1kΩ/1%
Fig. 15
VOUT
= 1.15 ×
⎜⎛1+
⎝
R1+ R2
R3
⎟⎞
⎠
It’s not recom mended to ch oose a resisto r larger th an
1KΩ to connect with FB to GND (R3 in F ig. 15), since a
larger resistor would carry parasitic capacitance and affect
the accurac y of V OUT detection. As well, the s witching
nodes such as LX pin or secondary side of XFMR should
be routed away from FB pin in such application as Fig. 20
to obtain accurate VOUT detection.
Leadtrend Technology Corporation
LD7271-DS-02, SEP. 2011
11
www.leadtrend.com.tw
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LD7271.PDF ] | |
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