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PDF ICS8536-01 Data sheet ( Hoja de datos )

Número de pieza ICS8536-01
Descripción 1-to-6 Crystal / LVCMOS / Differential-to-3.3V / 2.5V LVPECL Fanout Buffer
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Low Skew, 1-to-6, Crystal/ LVCMOS/
ICS8536-01
Differential-to-3.3V, 2.5V LVPECL Fanout Buffer
DATA SHEET
GENERAL DESCRIPTION
The ICS8536-01 is a lo w skew, high performance 1-to-6
Selectable Crystal, Single-Ended, or Diff erential Input-to-
3.3V, 2.5V LVPECL Fanout Buffer. The ICS8536-01 has
selectable cr ystal, single ended or diff erential clock inputs.
The single ended cloc k input accepts LVCMOS or LVTTL
input levels and tr anslates them to LVPECL levels. The
CLK1, nCLK1 pair can accept most standard diff erential
input levels. The output enable is inter nally synchronized to
eliminate runt pulses on the outputs dur ing asynchronous
assertion/deassertion of the cloc k enable pin.
Guaranteed output and par t-to-part skew characteristics
make the ICS8536-01 ideal f or those applications demanding
well defined perf ormance and repeatability.
FEATURES
• Six 3.3V, 2.5V LVPECL outputs
• Selectable crystal oscillator, differential CLK1, nCLK1 pair
or LVCMOS/LVTTL clock input
• CLK1, nCLK pair can accept the f ollowing differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Crystal frequency range: 12MHz - 40MHz
Output skew: 55ps (maximum) CLK1, nCLK1 @ 3.3V
Part-to-part skew: 450ps (maximum)
Additive phase jitter, RMS: 0.19ps (typical)
• Full 3.3V or 2.5V supply mode
• 0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) pac kages
BLOCK DIAGRAM
CLK_EN Pullup
CLK_SEL0 Pulldown
CLK_SEL1 Pulldown
XTAL_IN
XTAL_OUT
OSC
CLK0 Pulldown
CLK1 Pulldown
nCLK1 Pullup
00
01
1X
D
Q
LE
Q0
nQ0
6 LVPECL Outputs
Q5
nQ5
ICS8536-01 REVISION B AUGUST 17, 2012
1
PIN ASSIGNMENT
nQ2
Q2
VCC
nQ1
Q1
VEE
nQ0
Q0
CLK_SEL0
XTAL_IN
XTAL_OUT
CLK_EN
1
2
3
4
5
6
7
8
9
10
11
12
24 Q3
23 nQ3
22 VCC
21 Q4
20 nQ4
19 VCC
18 Q5
17 nQ5
16 CLK_SEL1
15 nCLK1
14 CLK1
13 CLK0
ICS8536-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm
package body
G Package
Top View
©2012 Integrated Device Technology, Inc.
http://www.Datasheet4U.com

1 page




ICS8536-01 pdf
ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
TABLE
4D.
DIFFERENTIAL
DC
CHARACTERISTICS,
V
CC
=
3.3V±5%
OR
2.5V±5%,
V
EE
=
0V,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical
IIH
nCLK1
Input High Current
CLK1
VCC = VIN = 3.465V or 2.625V
VCC = VIN = 3.465V
IIL
nVCLK1
Input Low Current
CLVK1
CC = 3.465V or 2.625V, VIN =00V
CC = 3.465V or 2.625V, VIN =50V
VPP
Peak-to-Peak Input Voltage;
NOTE 1
VCMR
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V .
IH
-1A5
-A
03.15
VEE +V0.5
Maximum
5
150
1V.
CC -V0.85
Units
µA
µA
µ
µ
TABLE
4E.
LVPECL
DC
CHARACTERISTICS,
VCC
=
3.3V±5%,
V
EE
=
0V,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum
VCC - 0.9
VCC - 1.7
1.0
Units
V
V
V
TABLE
4F.
LVPECL
DC
CHARACTERISTICS,
V
CC
=
2.5V±5%,
V
EE
=
0V,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
VCC - 1.4
VCC - 2.0
0.4
Typical
Maximum
VCC - 0.9
VCC - 1.5
1.0
Units
V
V
V
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Test Conditions
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
120 4z
50
7F
1W
Units
MH
Ω
p
m
ICS8536AG-01 REVISION B AUGUST 17, 2012
5
©2012 Integrated Device Technology, Inc.

5 Page





ICS8536-01 arduino
ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
OVERDRIVING THE CRYSTAL INTERFACE
The XTAL_IN input can be overdriven by an LVCMOS driver or
by one side of a diff erential driver through an AC coupling
capacitor. The XTAL_OUT pin can be left floating. The ampli-
tude of the input signal should be betw een 500mV and 1.8V
and the slew rate should not be less than 2V/nS . For 3.3V
LVCMOS inputs, the amplitude m ust be reduced from full s wing
to at least half the s wing in order to prevent signal interference
with the power rail and to reduce inter nal noise. Figure 3 shows
an example of the interface diagram for a high speed 3.3V
LVCMOS driver. This configuration requires that the sum of the
output impedance of the dr iver (Ro) and the ser ies resistance
(Rs) equals the tr ansmission line impedance. In addition,
matched termination at the cr ystal input will atten uate the
signal in half. This can be done in one of tw o ways. First, R1
and R2 in par allel should equal the tr ansmission line imped-
ance. For most 50Ω applications, R1 and R2 can be 100 Ω. This
can also be accomplished b y removing R1 and changing R2 to
50Ω. The values of the resistors can be increased to reduce the
loading for slower and weaker LVCMOS driver. Figure 3 sho ws
an example of the interface diagram for an LVPECL driver. This
is a standard LVPECL termination with one side of the dr iver
feeding the XTAL_IN input. It is recommended that all compo-
nents in the schematics be placed in the la yout. Though some
components might not be used, the y can be utilized for debug-
ging purposes. The datasheet specifications are char acterized
and guaranteed by using a quartz crystal as the input.
VCC
R1
100
Ro Rs Zo = 50 ohms
Zo = Ro + Rs
LVCMOS Driver
R2
100
XTAL_OUT
C1
XTAL_IN
.1uf
FIGURE 3A. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
XTAL_OUT
Zo = 50 ohms
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
C2
XTAL_IN
.1uf
FIGURE 3B. GENERAL DIAGRAM FOR LVPECL DRIVER TO XTAL INPUT INTERFACE
ICS8536AG-01 REVISION B AUGUST 17, 2012
11
©2012 Integrated Device Technology, Inc.

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