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MicrochipTechnology - 8K/16K2.5VSPIOBusSerialEEPROM

Numéro de référence 24LC080-IP
Description 8K/16K2.5VSPIOBusSerialEEPROM
Fabricant MicrochipTechnology 
Logo MicrochipTechnology 





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24LC080-IP fiche technique
25LC080/160
8K/16K 2.5V SPIBus Serial EEPROM
FEATURES
• SPI modes 0,0 and 1,1
• 3 MHz Clock Rate
• Single supply with programming operation down
to 2.5V
• Low Power CMOS Technology
- Max Write Current: 5 mA
- Read Current: 1.0 mA
- Standby Current: 1 µA typical
• Organization
- 1024 x 8 for 25LC080
- 2048 x 8 for 25LC160
• 16 Byte Page
• Sequential Read
• Self-timed ERASE and WRITE Cycles
• Block Write Protection
- Protect none, 1/4, 1/2, or all of Array
• Built-in Write Protection
- Power On/Off Data Protection Circuitry
- Write Latch
- Write Protect Pin
• High Reliability
- Endurance: 10M cycles (guaranteed)
- Data Retention: >200 years
- ESD protection: >4000 V
• 8-pin PDIP/SOIC Packages
• Temperature ranges supported
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 25LC080/160 are 8K
and 16K bit Serial Electrically Erasable PROMs. The
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
There are two other inputs that provide the end user
with additional flexibility. Communication to the device
can be paused via the hold pin (HOLD). While the
device is paused, transitions on its inputs will be
ignored, with the exception of chip select, allowing the
host to service higher priority interrupts. Also, write
operations to the Status Register can be disabled via
the write protect pin (WP).
PACKAGE TYPES
PDIP
CS 1
SO 2
WP 3
VSS 4
SOIC
CS
SO
WP
VSS
1
2
3
4
BLOCK DIAGRAM
Status
Register
8 VCC
7 HOLD
6 SCK
5 SI
8 VCC
7 HOLD
6 SCK
5 SI
HV Generator
I/O Control
Logic
Memory
Control
Logic
X
Dec
EEPROM
Array
Page Latches
WP
SI
SO
CS
SCK
HOLD
Vcc
Vss
Y Decoder
Sense Amp.
R/W Control
SPI is a trademark of Motorola.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21145D-page 1

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