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PDF FDMC7208S Data sheet ( Hoja de datos )
| Número de pieza | FDMC7208S | |
| Descripción | Dual N-Channel PowerTrench MOSFET | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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July 2013
FDMC7208S
Dual N-Channel PowerTrench® MOSFET
Q1: 30 V, 12 A, 9.0 mΩ Q2: 30 V, 16 A, 6.4 mΩ
Features
General Description
Q1: N-Channel
Max rDS(on) = 9.0 mΩ at VGS = 10 V, ID = 12 A
Max rDS(on) = 11.0 mΩ at VGS = 4.5 V, ID = 11 A
Q2: N-Channel
Max rDS(on) = 6.4 mΩ at VGS = 10 V, ID = 16 A
Max rDS(on) = 7.5 mΩ at VGS = 4.5 V, ID = 13.5 A
Termination is Lead-free and RoHS Compliant
This device inclu des two 30V N-Ch annel MOSFETs in a dual
Power 33 ( 3 mm X 3 mm MLP) package. Th e package is en-
hanced for exceptional thermal performance.
Applications
Computing
Communications
General Purpose Point of Load
Notebook System
Pin 1
G1 S1 S1 S1
D1
D2
G2 S2 S2 S2
Power 33
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 4)
TC = 25 °C
TA = 25 °C
(Note 3)
TA = 25 °C
TA = 25 °C
Q1 Q2
30 30
±20 ±12
22
121a
26
161b
60 80
21
1.91a
0.81c
21
1.91b
0.81d
-55 to +150
Units
V
V
A
mJ
W
°C
RθJA
RθJA
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
651a
1551c
651b
1551d
°C/W
Device Marking
FDMC7208S
Device
FDMC7208S
Package
Power 33
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2012 Fairchild Semiconductor Corporation
FDMC7208S Rev.C3
1
www.fairchildsemi.com
http://www.Datasheet4U.com
1 page  
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
10
ID = 12 A
8
VDD = 15 V
6
VDD = 10 V
4
VDD = 20 V
2
0
0 5 10
Qg, GATE CHARGE (nC)
15
Figure 7. Gate Charge Characteristics
2000
1000
Ciss
Coss
100
f = 1 MHz
VGS = 0 V
Crss
10
0.1
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure8. CapacitancevsDrain
to Source Voltage
30
40 100
10
TJ = 25 oC
TJ = 125 oC
TJ = 100 oC
1
0.01
0.1 1 10
tAV, TIME IN AVALANCHE (ms)
Figure 9.UnclampedInductive
Switching Capability
100
100
10
10
1 THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 155 oC/W
TA = 25 oC
0.01
0.01 0.1
DERIVED FROM
TEST DATA
1 10
VDS, DRAIN to SOURCE VOLTAGE (V)
1 ms
10 ms
100 ms
1s
10 s
DC
100
Figure 10. Forward Bias Safe
Operating Area
SINGLE PULSE
RθJA = 155 oC/W
TA = 25 oC
1
0.5
10-3
10-2
10-1
100
101
t, PULSE WIDTH (sec)
Figure 11. Single Pulse Maximum Power Dissipation
100
1000
©2012 Fairchild Semiconductor Corporation
FDMC7208S Rev.C3
5
www.fairchildsemi.com
5 Page 
Dimensional Outline and Pad Layout
©2012 Fairchild Semiconductor Corporation
FDMC7208S Rev.C3
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet FDMC7208S.PDF ] | |
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