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PDF 24FC515 Data sheet ( Hoja de datos )
| Número de pieza | 24FC515 | |
| Descripción | 512KI2CCMOSSerialEEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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24AA515/24LC515/24FC515
512K I2C™ CMOS Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
24AA515 1.8-5.5V
24LC515 2.5-5.5V
24FC515 2.5-5.5V
†100 kHz for VCC < 2.5V.
Max Clock
Frequency
400 kHz†
400 kHz
1 MHz
Temp
Ranges
I
I
I
Features
• Low-power CMOS technology
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 µA at 5.5V
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I2C™ compatible
• Cascadable for up to four devices
• Self-timed ERASE/WRITE cycle
• 64-byte Page Write mode available
• 5 ms max write cycle time
• Hardware write-protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt Trigger inputs for noise suppression
• 100,000 erase/write cycles
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP, SOIC packages
• Temperature ranges:
- Industrial (I):
-40°C to +85°C
Description
The Microchip Technology Inc. 24AA515/24LC515/
24FC515 (24XX515*) is a 64K x 8 (512K bit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low power applications
such as personal communications or data acquisition.
This device has both byte write and page write capabil-
ity of up to 64 bytes of data. This device is capable of
both random and sequential reads. Reads may be
sequential within address boundaries 0000h to 7FFFh
& 8000h to FFFFh. Functional address lines allow up to
four devices on the same data bus. This allows for up
to 2 Mbits total system EEPROM memory. This device
is available in the standard 8-pin plastic DIP and SOIC
packages.
Package Type
PDIP
A0 1
A1 2
A2 3
VSS 4
SOIC
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
8 VCC
7 WP
6 SCL
5 SDA
Block Diagram
A0 A1 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
I/O
SCL
SDA
VCC
VSS
EEPROM
Array
Page Latches
YDEC
Sense AMP
R/W Control
24XX515 is used in this document as a generic part number
for the 24AA515/24LC515/24FC515 devices.
2003 Microchip Technology Inc.
Preliminary
DS21673C-page 1
1 page  
24AA515/24LC515/24FC515
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name PDIP SOIC
Function
A0 1
A1 2
A2 3
VSS
SDA
SCL
WP
VCC
4
5
6
7
8
1 User Configurable Chip Select
2 User Configurable Chip Select
3 Non-Configurable Chip Select.
This pin must be hard wired to
logical 1 state (VCC). Device
will not operate with this pin
left floating or held to logical 0
(VSS).
4 Ground
5 Serial Data
6 Serial Clock
7 Write-Protect Input
8 +1.8 to 5.5V (24AA515)
+2.5 to 5.5V (24LC515)
+4.5 to 5.5V (24FC515)
2.1 A0, A1 Chip Address Inputs
The A0, A1 inputs are used by the 24XX515 for multiple
device operations. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. If left
unconnected, these inputs will be pulled down
internally to VSS.
2.2 A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to VCC in order for this device to operate.
2.3 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.4 Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.5 Write-Protect (WP)
This pin can be connected to either VSS, VCC or left
floating. An internal pull-down resistor on this pin will
keep this device in the unprotected state if left floating.
If tied to VSS or left floating, normal memory operation
is enabled (read/write the entire memory 0000h-
FFFFh).
If tied to VCC, write operations are inhibited. Read
operations are not affected.
3.0 FUNCTIONAL DESCRIPTION
The 24XX515 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX515 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
2003 Microchip Technology Inc.
Preliminary
DS21673C-page 5
5 Page 
24AA515/24LC515/24FC515
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
8.1 Current Address Read
The 24XX515 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24XX515 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a Stop condition and the
24XX515 discontinues transmission (Figure 8-1).
FIGURE 8-1:
CURRENT ADDRESS
READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A CONTROL
R BYTE
T
S
1
0
1
0
BAA
010
1
A
C
K
DATA
BYTE
S
T
O
P
P
N
O
A
C
K
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX515 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
Start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then, the master issues the
control byte again but with the R/W bit set to a one. The
24XX515 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a Stop condition which
causes the 24XX515 to discontinue transmission
(Figure 8-2). After a random Read command, the inter-
nal address counter will point to the address location
following the one that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX515 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX515 to trans-
mit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge
but will generate a Stop condition. To provide sequen-
tial reads, the 24XX515 contains an internal address
pointer which is incremented by one at the completion
of each operation. This address pointer allows half the
memory contents to be serially read during one opera-
tion. Sequential read address boundaries are 0000h to
7FFFh and 8000h to FFFFh. The internal address
pointer will automatically roll over from address 7FFF to
address 0000 if the master acknowledges the byte
received from the array address 7FFF. The internal
address counter will automatically roll over from
address FFFFh to address 8000h if the master
acknowledges the byte received from the array
address FFFFh.
2003 Microchip Technology Inc.
Preliminary
DS21673C-page 11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 24FC515.PDF ] | |
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