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PDF 24FC32-IP Data sheet ( Hoja de datos )
| Número de pieza | 24FC32-IP | |
| Descripción | 32K5.0V1MHzI2CSmartSerialEEPROM | |
| Fabricantes | MicrochipTechnology | |
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24FC32
32K 5.0V 1 MHz I2C™ Smart Serial™ EEPROM
FEATURES
• Voltage operating range: 4.5V to 5.5V
- Maximum write current 3 mA at 5.5V
- Maximum read current 150 µA at 5.5V
- Standby current 1 µA typical
• 1 MHz SE2.bus two wire protocol
• Self-timed write cycle (including auto-erase)
• Power on/off data protection circuitry
• Endurance:
- 10,000,000 Erase/Write cycles guaranteed
for a 4K block
- 1,000,000 E/W cycles guaranteed for a 28K
block
• 8-byte page, or byte modes available
• 1 page x 8 line input cache (64 bytes) for fast write
loads
• Schmitt trigger inputs for noise suppression
• 2 ms typical write cycle time, byte or page
• Up to 8 chips may be connected to the same bus
for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
- Commercial (C):
0˚C to +70˚C
- Industrial (I):
-40˚C to +85˚C
DESCRIPTION
The Microchip Technology Inc. 24FC32 is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM (EEPROM) with
a high-speed 1 MHz SE2.bus whose protocol is
functionally equivalent to the industry-standard I2C bus.
This device has been developed for advanced, low
power applications such as personal communications
or data acquisition. The 24FC32 features an input
cache for fast write loads with a capacity of eight 8-byte
pages, or 64 bytes. It also features a fixed 4K-bit block
of ultra-high endurance memory for data that changes
frequently. The 24FC32 is capable of both random and
sequential reads up to the 32K boundary. Functional
address lines allow up to 8 - 24FC32 devices on the
same bus, for up to 256K bits address space. The
24FC32 is available in the standard 8-pin plastic DIP
and 8-pin surface mount SOIC package.
PACKAGE TYPES
PDIP
A0
A1
A2
VSS
1
2
3
4
SOIC
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 NC
6 SCL
5 SDA
8 VCC
7 NC
6 SCL
5 SDA
BLOCK DIAGRAM
A0..A2
HV GENERATOR
I/O
CONTROL
LOGIC
I/O
SCL
SDA
MEMORY
CONTROL
LOGIC
XDEC
VCC
VSS
EEPROM
ARRAY
PAGE LATCHES
CACHE
YDEC
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
Smart Serial is a trademark of Microchip Technology Inc.
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS21126B-page 3-1
1 page  
3.6 Device Addressing
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a four bit control code; for the 24FC32 this
is set as 1010 binary for read and write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device
to select which of the eight devices are to be accessed.
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte (R/W)
defines the operation to be performed. When set to a
one a read operation is selected, and when set to a
zero a write operation is selected. The next two bytes
received define the address of the first data byte
(Figure 3-3). Because only A11..A0 are used, the upper
four address bits must be zeros. The most significant bit
of the most significant byte of the address is transferred
first. Following the start condition, the 24FC32 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24FC32 will select a read or
write operation.
24FC32
FIGURE 3-2:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W A
1 0 1 0 A2 A1 A0
X = Don’t care
Operation
Read
Write
Control
Code
Device Select
1010
1010
Device Address
Device Address
R/W
1
0
FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL
BYTE
ADDRESS
BYTE 1
1
0
1
0
A
2
A
1
A
0
R/W
Slave
Address
Device
Select
Bits
0
0
0
0
A
11
A
10
A
9
A
8
ADDRESS
BYTE 0
A
7
•
•
•
•
•
•
A
0
© 1996 Microchip Technology Inc.
DS21126B-page 3-5
5 Page 
8.0 PIN DESCRIPTIONS
8.1 A0, A1, A2 Chip Address Inputs
The A0..A2 inputs are used by the 24FC32 for multiple
device operation and conform to the two-wire bus
standard. The levels applied to these pins define the
address block occupied by the device in the address
map. A particular device is selected by transmitting the
corresponding bits (A2, A1, A0) in the control byte
(Figure 3-3).
8.2 SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 1KΩ, must consider total bus
capacitance and maximum rise/fall times).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
8.3 SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
24FC32
© 1996 Microchip Technology Inc.
DS21126B-page 3-11
11 Page | ||
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| PDF Descargar | [ Datasheet 24FC32-IP.PDF ] | |
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