24CO24-SN Datasheet PDF - MicrochipTechnology
| Part Number | 24CO24-SN | |
| Description | 2K 2.5V I2C Serial EEPROM | |
| Manufacturers | MicrochipTechnology | |
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M 24LC024/24LC025
2K 2.5V I2C™ Serial EEPROM
FEATURES
• Single supply with operation from 2.5 to 5.5V
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
• Organized as a single block of 128 bytes (256 x 8)
• Hardware write protection for entire array
(24LC024)
• 2-wire serial interface bus, I2C compatible
• 100kHz and 400kHz compatibility
• Page-write buffer for up to 16 bytes
• Self-timed write cycle (including auto-erase)
• 3.5 ms typical write cycle time for page write
• Address lines allow up to eight devices on bus
• 10,000,000 erase/write cycles guaranteed
• ESD protection > 4,000V
• Data retention > 200 years
• 8-pin PDIP, SOIC or TSSOP packages
• Available for extended temperature ranges
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24LC024/24LC025 is a
2K bit Serial Electrically Erasable PROM with a voltage
range of 2.5V to 5.5V. The device is organized as a
single block of 256 x 8-bit memory with a 2-wire serial
interface. Low current design permits operation with
typical standby and active currents of only 10 µA and 1
mA respectively. The device has a page-write capability
for up to 16 bytes of data. Functional address lines
allow the connection of up to eight 24LC024/24LC025
devices on the same bus for up to 16K bits of contigu-
ous EEPROM memory. The device is available in the
standard 8-pin PDIP, 8-pin SOIC (150 mil), and TSSOP
packages.
PACKAGE TYPES
PDIP/SOIC
A0 1
A1 2
A2 3
Vss 4
8 Vcc
7 WP*
6 SCL
5 SDA
TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP*
6 SCL
5 SDA
*WP pin available only on 24LC024. This
pin has no internal connection on 24LC025
BLOCK DIAGRAM
A0 A1 A2
WP*
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
SDA SCL
VCC
VSS
EEPROM
Array
Write Protect
Circuitry
YDEC
SENSE AMP
R/W CONTROL
*WP pin available only on 24LC024. This
pin has no internal connection on 24LC025
© 1997 Microchip Technology Inc.
Preliminary
DS21210A-page 1
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24LC024/24LC025
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
4.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
4.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
4.5 Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24LC024/24LC025 does not generate
any acknowledge bits if an internal pro-
gramming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 4-2).
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
SCL (A) (B)
(C)
(D)
(C) (A)
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
FIGURE 4-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL 1 2 3 4 5 6 7 8 9 1 2 3
STOP
CONDITION
SDA
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
© 1997 Microchip Technology Inc.
Preliminary
DS21210A-page 5
Preview 5 Page |
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| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 24CO24-SN.PDF Datasheet ] | |
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| Part Number | Description | MFRS |
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