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PDF THC63LVD827 Data sheet ( Hoja de datos )
| Número de pieza | THC63LVD827 | |
| Descripción | Low Power / Small Package / 24Bit Color LVDS Transmitter | |
| Fabricantes | THine | |
| Logotipo |  |
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THC63LVD827_Rev.1.00_E
THC63LVD827
LOW POWER / SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER
General Description
The THC63LVD827 transmitter is designed to support
pixel data transmission between Host and Flat Panel
Display and Dual Link transmission between Host and
Flat Panel Display up to 1080p/1920x1440 resolutions.
The THC63LVD827 converts 27bits (RGB 8 bits +
Hsync, Vsy nc, DE) of CMOS/TTL dat a into L VDS
(Low Voltage Di fferential Signali ng) dat a stream. The
transmitter can be programmed for rising edge or falling
edge clocks through a dedicated pin.
F or dual LVDS out, LVDS clock frequency of
87MHz, 51bits of RGB data are transmitted at an effec-
tive rate of 609Mbps per LVDS channel.
For sing le L VDS o ut, L VDS cl ock frequency of
174MHz, 27bits of RGB data are transmitted at an
effective rate of 1218Mbps per LVDS channel.
21bits (RGB 6 bits + Hsync, Vsync, DE) mode is also
selectable for 6bit color transmission with lower power.
Block Diagram
Features
• Low power 1.8V CMOS design
• 7mm x 7mm/72pin/0.65mm pitch/TFBGA package
applicable to non-HDI PCB.
• Wide dot clock range, 10-174MHz, suited for
TV Signal: up to 1080p(74.25MHz dual)
PC Signal: up to 1920x1440(86MHz dual)
• Supports 1.8V single power supply
• 1.8V/2.5V/3.3V TTL/CMOS inputs are supported
by setting IOVCC=1.8V/2.5V/3.3V
• LVDS swing reducible by RS-pin to reduce both
EMI and power consumption
• PLL requires No external components
• Flexible Input/Output mode
1. Single in / Dual LVDS out
2. Single in / Single LVDS out
3. Double edge Single in / Dual LVDS out
• 2 LVDS data mapping to simplify PCB layout
• Power down mode
• Input clock triggering edge selectable by R/F pin
• 6bit / 8bit modes selectable by 6B/8B pin
TTL/CMOS Inputs
R1[7:0]
G1[7:0]
B1[7:0]
24
28
HSYNC
VSYNC
DE
3
R/F
RS
MAP
MODE
O/E
DDRN
/PDWN
PRBS
6B/8B
TRANSMITTER CLOCK IN
10 to 174MHz
(Single in /Dual out : 20 to 174MHz)
Copyright©2012 THine Electronics, Inc.
28
PLL
1/18
TA1 +/-
TB1 +/-
TC1 +/-
TD1 +/-
TA2 +/-
TB2 +/-
TC2 +/-
TD2 +/-
LVDS Outputs
1st Link
LVDS Outputs
2nd Link
TCLK1 +/-
TCLK2 +/-
10 to 174MHz
THine Electronics, Inc.
http://www.Datasheet4U.com
1 page  
THC63LVD827_Rev.1.00_E
Absolute Maximum Ratings
Supply Voltage (IOVCC)
Supply Voltage (VCC, PLLVCC, LVDSVCC)
CMOS/TTL Input Voltage
LVDS Transmitter Output Voltage
Output Current
Junction Temperature
Storage Temperature Range
Reflow Peak Temperature / Time
Maximum Power Dissipation @+25 °C
-0.3V ~ +4.0V
-0.3V ~ +2.1V
-0.3V ~ (IOVCC+ 0.3V)
-0.3V ~ (LVDSVCC + 0.3V)
-50mA ~ 50mA
+125 °C
-55 °C ~ +125 °C
+260 °C / 10sec.
1.3W
Recommended Operating Conditions
Parameter
Supply Voltage (IOVCC)
Supply Voltage (PLLVCC / LVDSVCC / VCC)
Operating Ambient Temperature (Ta)
Clock
Frequency
MODE=L
Dual-out
Single Edge Input
(DDRN=H)
Double Edge Input
(DDRN=L)
Input
LVDS Output
Input
LVDS Output
MODE=H
Single-out
Input
LVDS Output
Min Typ Max Units
1.62 1.8 / 2.5 / 3.3 3.6 V
1.62 1.8 1.98 V
-40 85 °C
20 174 MHz
10 87 MHz
10 174 MHz
10 174 MHz
10 174 MHz
10 174 MHz
Copyright©2012 THine Electronics, Inc.
5/18
THine Electronics, Inc.
5 Page 
THC63LVD827_Rev.1.00_E
AC Timing Diagrams (Continued)
tTOP2
tTOP3
tTOP4
tTOP5
tTOP6
tTOP0
tTOP1
Tyx+/-
Tyx6 Tyx5 Tyx4 Tyx3 Tyx2 Tyx1 Tyx0 Tyx6 Tyx5 Tyx4 Tyx3 Tyx2 Tyx1
TCLKx+
x = 1,2
y = A,B,C,D
Vdiff = 0V
Vdiff = 0V
tTCOP
Note:
Vdiff = (Tyx+) - (Tyx-), (TCLKx+) - (TCLKx-)
Fig6. LVDS Output Data Position
Copyright©2012 THine Electronics, Inc.
11/18
THine Electronics, Inc.
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet THC63LVD827.PDF ] | |
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