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PDF A3942 Data sheet ( Hoja de datos )
| Número de pieza | A3942 | |
| Descripción | Quad High-Side Gate Driver | |
| Fabricantes | ALLEGRO | |
| Logotipo |  |
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A3942
Quad High-Side Gate Driver
for Automotive Applications
Features and Benefits
▪ Drives four N-channel high-side MOSFETS
▪ Charge pump for 100% duty cycle operation
▪ Serial and discrete inputs
▪ SPI port for control and fault diagnostics
▪ 4.5 to 60 V input voltage range
▪ Sleep function for minimum power drain
▪ Thin profile 38-lead TSSOP with internally fused leads for
enhanced thermal dissipation
▪ Lead (Pb) free
▪ Device protection features:
▫ Short-to-ground detection (latched)
▫ Short-to-battery protection (latched)
▫ Open load detection (latched)
▫ VDD undervoltage lockout
▫ VCP undervoltage lockout
▫ Thermal monitor
Package: 38 pin TSSOP (suffix LG)
Description
The A3942 is a highly-integrated gate driver IC that can drive
up to four N-Channel MOSFETs in a high-side configuration.
The device is designed to withstand the harsh environmental
conditions and high reliability standards of automotive
applications.
Serial Peripheral Interface (SPI) compatibility makes the device
easily integrated into existing applications. The MOSFETs in
such applications are typically used to drive gasoline or diesel
engine management actuators, transmission actuators, body
control actuators and other general-purpose automotive or
industrial loads. In particular, the A3942 is suited for driving
glow plugs, valves, solenoids, and other inductive loads in
engine management and transmission systems.
The device is available in a 38-lead thin (1.20 mm maximum
overall height) TSSOP package with six pins that are fused
internally to provide enhanced thermal dissipation (package
LG). It is lead (Pb) free with 100% matte tin leadframe
plating.
3942-DS, Rev. 5
Approximate Scale 1:1
VDD
System
Control
Logic
Typical Application
CP1 CP2
VDD
IREF
VREG
CP3 CP4
VCP
VBB
D1
FAULTZ
SDO
A3942
G1
S1
SDI
CSZ
SCLK
RESETZ
ENB
D2
G2
S2
D3
IN1 G3
IN2 S3
IN3
D4
IN4
G4
GND GND GND GND GND GND S4
VBAT
http://www.Datasheet4U.com
1 page  
A3942
Quad High-Side Gate Driver
for Automotive Applications
ELECTRICAL CHARACTERISTICS (continued) Valid at –40°C ≤ TJ ≤ 150°C, C12 = C34 = 0.47 μF, CCP = 1 μF,
RREF = 60.4 kΩ, and VBB within limits, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min. Typ.
Logic Input Hysteresis
Vhys
CSZ pin
0.1 ×
VDD
––
––
Logic Input Current1
II(HI) SDI and SCLK Pins VI = VDD = 5.5 V
All other pins
CSZ pin
––
––
––
II(LO)
SDI and SCLK Pins
All other pins
VI = 0 V
––
––
Logic Output Voltage, SDO Pin
(CMOS push-pull circuit)
FAULTZ Pin Active (Low) Voltage
FAULTZ Pin Inactive (High) Current
VOUT(HI) IOUT = –1 mA
VOUT(LO)
VFAULTZ(LO)
IFAULTZ(HI)
IOUT = 1 mA
IFAULTZ = 1 mA, VDD = 1.5 V, VBB = 4.5 V
VFAULTZ = 5 V
VDD
– 0.5
–
–
–
–V
–
–
–
Drivers
Gate Voltage, High
VG(HI)
Measured relative to Sx pin, capacitive load–fully
charged
VCP
–1
–V
Gate Voltage, Low
VG(LO)
Measured relative to Sx pin, capacitive load–fully
discharged
–
–
Peak Gate Current1,2
Propagation Delay
Gate-to-Source Resistance
Gate-to-Source Zener Diode Voltage
Drain Leakage Current
IG(HI)
IG(LO)
tp(on)
tp(off)
RGS
VGS(Z)
IDlkg
RG = 0 Ω, 1 V ≤ VGS ≤
4 V, VSx = VBB
VBB = 4.5 V, VCP = 9 V
VBB ≥ 9 V, VCP = 13 V
RG = 0 Ω, VGS = 1 V, VSx = 0 V
RG = 0 Ω, 2 V ≤ VGS ≤ 4 V, VSx = 0 V
From 90% VINx to VGx – VSx = 200 mV
From 10% VINx to VCP – VGx = 200 mV
RESETZ pin held low; VGSZ = 10 V
IG = 2 mA
RESETZ pin held low, VBB = VDx = 60 V
RESETZ pin held low,
VBB = VDx = 36 V
TJ = 150°C
TJ = 25°C
–10 –
–15 –
10 –
25 –
– 0.6
– 0.6
300 500
15 –
––
––
––
Max.
10
5
100
–100
–5
–10
DD
0.4
0.4
10
CP
0.1
–
–
–
–
–
–
800
18
10
5
1
Units
V
μA
μA
μA
μA
μA
μA
V
V
V
μA
V
V
mA
mA
mA
mA
μs
μs
kΩ
V
μA
μA
μA
Continued on the next page...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page 
A3942
Quad High-Side Gate Driver
for Automotive Applications
on a channel-specific basis, according to the following
table:
D4 Setting
0
1
Handling of
Off-State Faults
Registered
Ignored
D5 Read Enable Bit This bit enables or disables read-
ing on the serial inputs, according to the following
table:
D5 Setting
0
1
Handling of
Serial Input
Ignored
Registered
D6, D7 Address MSB and LSB Bits (Input and Out-
put Fault registers) For channel-specific bits, these
bits are used to specify which channel is indicated.
The channel-specific bits are:
Register
Input
Output
Channel-Specific Bits
D0, D1, D2, D3, D4
D0, D1, D2
These bits determine the channel, according to the fol-
lowing table:
D7 D6 Channel Selected
00
1
01
2
10
3
11
4
Output FAULT Register
D0 Short-to-Ground (STG) Fault Bit The voltage
from drain to source for each MOSFET is monitored.
An internal current source sinks IDx from the Dx pins
to set the VDS threshold for each channel, the level at
which an STG fault condition is evaluated.
The A3942 enables monitoring for an STG fault after
the MOSFET is turned on and the turn-on blank time,
tON , expires. (The MOSFET is turned on via the Input
register D0 bit, ORed with the INx discrete input pin
for the channel of the MOSFET, and tON is set by
Input register D1 and D2 bits). If the MOSFET gate-
to-source voltage exceeds the VDS threshold, then
an STG fault will be registered for that channel, the
MOSFET gate will be discharged, and the FAULTZ
pin will be set low (active).
An STG fault is latched until cleared (using the Input
register D3 bit). In the meantime, the other channels
can continue to operate normally.
D1 Short to Battery (STB) Fault Bit When a chan-
nel turns off, STB fault detection is blanked for tOFF.
Subsequently, if the Sx pin voltage exceeds the VDS
threshold voltage for that channel, an STB fault is
latched. The output for that channel is disabled until
the fault is either cleared (via the Input register D3 bit)
or the off-state fault diagnostics are masked (via the
Input register D4 bit).
Because the output is disabled, there is no active
pull-down during an STB event. Note that, in general,
when the voltage on SX is high enough to trip the STB
comparator, it also trips the OL comparator, and both
the STB and the OL faults are latched.
D2 Open Load (OL) Fault Bit When a channel turns
off, the OL fault is blanked for tOFF. A small bias
current, IOL, is sourced to the Sx pin of the channel.
There it divides between RSx and the load. If the load
is open, the Sx voltage will rise above the OL fault
detection threshold. In that case, the output is disabled
until the fault is cleared (via the Input register D3 bit)
or the off-state fault diagnostics are masked (via the
Input register D4 bit).
D3 Thermal Warning Bit A die temperature monitor
is integrated on the A3942 chip. If the die temperature
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet A3942.PDF ] | |
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