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PDF 24C16 Data sheet ( Hoja de datos )
| Número de pieza | 24C16 | |
| Descripción | 16K-Bit Standard 2-Wire Bus Interface Serial EEPROM | |
| Fabricantes | FairchildSemiconductor | |
| Logotipo |  |
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 1. 16KBit, EEPROM Memory, 8 Pin  Hay una vista previa y un enlace de descarga de 24C16 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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NM24C16/17 – 16K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
February 2000
General Description
The NM24C16/17 devices are 16,384 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the Standard IIC 2-wire protocol and are designed to
minimize device pin count, and simplify PC board layout require-
ments.
The upper half (upper 8Kbit) of the memory of the NM24C17 can be
write protected by connecting the WP pin to VCC. This section of
memory then becomes unalterable unless WP is switched to VSS.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the NM24C32 or NM24C65 datasheets for more infor-
mation.)
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption.
Block Diagram
VCC
VSS
WP
SDA
SCL
START
STOP
LOGIC
SLAVE ADDRESS
REGISTER
CONTROL
LOGIC
Features
I Extended operating voltage 2.7V – 5.5V
I 400 KHz clock frequency (F) at 2.7V - 5.5V
I 200µA active current typical
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I IIC compatible interface
– Provides bi-directional data transfer protocol
I Schmitt trigger inputs
I Sixteen byte page write mode
– Minimizes total write time per byte
I Self timed write cycle
Typical write cycle time of 6ms
I Hardware Write Protect for upper half (NM24C17 only)
I Endurance: 1,000,000 data changes
I Data retention greater than 40 years
I Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
I Available in three temperature ranges
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
H.V. GENERATION
TIMING &CONTROL
XDEC
E2PROM
ARRAY
WORD
ADDRESS
COUNTER
R/W YDEC
CK
DIN
DATA REGISTER
DOUT
© 1998 Fairchild Semiconductor Corporation
NM24C16/17 Rev. G
1
DS500072-1
www.fairchildsemi.com
1 page  
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
VCC x 0.1 to VCC x 0.9
10 ns
Input & Output Timing Levels VCC x 0.3 to VCC x 0.7
Output Load
1 TTL Gate and CL = 100 pF
AC Testing Input/Output Waveforms
0.9VCC
0.1VCC
0.7VCC
0.3VCC
DS500072-6
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
Min Max
400 KHz
Min Max
fSCL SCL Clock Frequency
TI Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
100
100
400
50
tAA SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9
tBUF Time the Bus Must Be Free before
a New Transmission Can Start
4.7
1.3
tHD:STA
tLOW
tHIGH
tSU:STA
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
4.0
4.7
4.0
4.7
0.6
1.5
0.6
0.6
tHD:DAT
Data in Hold Time
20
20
tSU:DAT
Data in Setup Time
250
100
tR SDA and SCL Rise Time
1 0.3
tF SDA and SCL Fall Time
300 300
tSU:STO
Stop Condition Setup Time
4.7
0.6
tDH Data Out Hold Time
300
50
tWR
(Note 3)
Write Cycle Time - NM24C16/17
- NM24C16/17L, NM24C16/17LZ
10
15
10
15
Units
KHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C16/17 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.
Bus Timing
tF
tLOW
SCL
SDA
tSU:STA
tHD:STA
;;IN
SDA
OUT
tAA
tHIGH
tHD:DAT
tR
tLOW
tSU:DAT
tDH
tSU:STO
tBUF
DS500072-7
NM24C16/17 Rev. G
5 www.fairchildsemi.com
5 Page 
Write Operations
BYTE WRITE
For a write operation a second address field is required which is
a word address that is comprised of eight bits and provides access
to any one of the 256 bytes in the selected page of memory. Upon
receipt of the byte address the NM24C16/17 responds with an
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the NM24C16/
17 begins the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the NM24C16/17 inputs are
disabled, and the device will not respond to any requests from the
master for the duration of tWR. Refer to Figure 4 for the address,
acknowledge and data transfer sequence.
PAGE WRITE
To minimize write cycle time, NM24C16/17 offer Page Write
feature, by which, up to a maximum of 16 contiguous bytes
locations can be programmed all at once (instead of 16 individual
byte writes). To facilitate this feature, the memory array is orga-
nized in terms of “Pages.” A Page consists of 16 contiguous byte
locations starting at every 16-Byte address boundary (for ex-
ample, starting at array address 0x00, 0x10, 0x20 etc.). Page
Write operation limits access to byte locations within a page. In
other words a single Page Write operation will not cross over to
locations on another page but will “roll over” to the beginning of the
page whenever end of Page is reached and additional locations
are a continued to be accessed. A Page Write operation can be
initiated to begin at any location within a page (starting address of
the Page Write operation need not be the starting address of a
Page).
Page Write is initiated in the same manner as the Byte Write
operation; but instead of terminating the cycle after transmitting
the first data byte, the master can further transmit up to 15 more
bytes. After the receipt of each byte, NM24C16/17 will respond
with an acknowledge pulse, increment the internal address counter
to the next address and is ready to accept the next data. If the
master should transmit more than sixteen bytes prior to generat-
ing the STOP condition, the address counter will “roll over” and
previously written data will be overwritten. As with the Byte Write
operation, all inputs are disabled until completion of the internal
write cycle. Refer to Figure 5 for the address, acknowledge and
data transfer sequence.
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host’s
write operation the NM24C16/17 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write operation.
If the NM24C16/17 is still busy with the write operation no ACK will
be returned. If the NM24C16/17 has completed the write operation
an ACK will be returned and the host can then proceed with the
next read or write operation.
Write Protection (NM24C17 Only)
Programming of the upper half (upper 8Kbit) of the memory will not
take place if the WP pin of the NM24C17 is connected to VCC. The
NM24C17 will respond to slave and byte addresses; but if the
memory accessed is write protected by the WP pin, the NM24C17
will not generate an acknowledge after the first byte of data has
been received, and thus the program cycle will not be started when
the stop condition is asserted.
Byte Write (Figure 4)
Bus Activity:
Master
SDA Line
Bus Activity:
EEPROM
S
T
A SLAVE
R ADDRESS
T
A
C
K
WORD
ADDRESS
A
C
K
DATA
S
T
O
P
A
C
K
DS500072-14
Page Write (Figure 5)
Bus Activity:
Master
SDA Line
S
T
A SLAVE
R ADDRESS
T
Bus Activity:
EEPROM
WORD ADDRESS (n)
AA
CC
KK
DATA n
DATA n + 1
AA
CC
KK
DATA n + 15
S
T
O
P
A
C
K
DS500072-15
NM24C16/17 Rev. G
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet 24C16.PDF ] | |
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