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| Número de pieza | ADSP-21060LC | |
| Descripción | SHARC Processor | |
| Fabricantes | ANALOG DEVICES | |
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SHARC Processor
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
SUMMARY
High performance signal processor for communications,
graphics and imaging applications
Super Harvard Architecture
4 independent buses for dual data fetch, instruction fetch,
and nonintrusive I/O
32-bit IEEE floating-point computation units—multiplier,
ALU, and shifter
Dual-ported on-chip SRAM and integrated I/O peripherals—a
complete system-on-a-chip
Integrated multiprocessing features
240-lead thermally enhanced MQFP_PQ4 package, 225-ball
plastic ball grid array (PBGA), 240-lead hermetic CQFP
package
RoHS compliant packages
KEY FEATURES—PROCESSOR CORE
40 MIPS, 25 ns instruction rate, single-cycle instruction
execution
120 MFLOPS peak, 80 MFLOPS sustained performance
Dual data address generators with modulo and bit-reverse
addressing)
Efficient program sequencing with zero-overhead looping:
Single-cycle loop setup
IEEE JTAG Standard 1149.1 Test Access Port and on-chip
emulation
32-bit single-precision and 40-bit extended-precision IEEE
floating-point data formats or 32-bit fixed-point data
format
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 48-BIT
DAG1
DAG2
8 4 32 8 4 24
PROGRAM
SEQUENCER
PM ADDRESS BUS
DM ADDRESS BUS
24
32
BUS
CONNECT
(PX)
PM DATA BUS
48
DM DATA BUS 40/32
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
ADDR
DATA
DATA
ADDR
ADDR
DATA
DATA
ADDR
IOD IOA
48 17
S
JTAG
TEST AND
EMULATION
7
EXTERNAL
PORT
ADDR BUS
MUX
32
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
48
HOST PORT
DATA
REGISTER
FILE
MULT 16 40-BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
LINK PORTS
(6)
I/O PROCESSOR
4
6
6
36
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. F
Information furnished by Analog Devices is believed t o be ac curate and reli able.
However, no r esponsibility is assumed by Analo g Dev ices for its use, n or fo r any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or pa tent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel : 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
http://www.Datasheet4U.com
1 page  
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-2106x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With its separate program and data
memory buses and on-chip instruction cache, the processor can
simultaneously fetch two operands and an instruction (from the
cache), all in a single cycle.
Instruction Cache
The ADSP-2106x includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-2106x’s two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-2106x contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any mem-
ory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of
parallel operations, for concise programming. For example, the
ADSP-2106x can conditionally execute a multiply, an add, a
subtract and a branch, all in a single instruction.
MEMORY AND I/O INTERFACE FEATURES
The ADSP-2106x processors add the following architectural
features to the SHARC family core.
Dual-Ported On-Chip Memory
The ADSP-21062/ADSP-21062L contains two megabits of on-
chip SRAM, and the ADSP-21060/ADSP-21060L contains
4M bits of on-chip SRAM. The internal memory is organized as
two equal sized blocks of 1M bit each for the ADSP-21062/
ADSP-21062L and two equal sized blocks of 2M bits each for
the ADSP-21060/ADSP-21060L. Each can be configured for dif-
ferent combinations of code and data storage. Each memory
block is dual-ported for single-cycle, independent accesses by
the core processor and I/O processor or DMA controller. The
dual-ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle.
On the ADSP-21062/ADSP-21062L, the memory can be config-
ured as a maximum of 64k words of 32-bit data, 128k words of
16-bit data, 40k words of 48-bit instructions (or 40-bit data), or
combinations of different word sizes up to two megabits. All of
the memory can be accessed as 16-bit, 32-bit, or 48-bit words.
On the ADSP-21060/ADSP-21060L, the memory can be config-
ured as a maximum of 128k words of 32-bit data, 256k words of
16-bit data, 80k words of 48-bit instructions (or 40-bit data), or
combinations of different word sizes up to four megabits. All of
the memory can be accessed as 16-bit, 32-bit or 48-bit words.
A 16-bit floating-point storage format is supported, which effec-
tively doubles the amount of data that can be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit float-
ing-point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one ofthe
data operands is transferred to or from off-chip, via the
ADSP-2106x’s external port.
On-Chip Memory and Peripherals Interface
The ADSP-2106x’s external port provides the processor’s inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-2106x’s unified
address space. The separate on-chip buses—for PM addresses,
PM data, DM addresses, DM data, I/O addresses, and I/O
data—are multiplexed at the external port to create an external
system bus with a single 32-bit address bus and a single 48-bit
(or 32-bit) data bus.
Addressing of external memory devices is facilitated by on-chip
decoding of high-order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-2106x
provides programmable memory wait states and external mem-
ory acknowledge controls to allow interfacing to DRAM and
peripherals with variable access, hold and disable time
requirements.
Host Processor Interface
The ADSP-2106x’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with lit-
tle additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-2106x’s exter-
nal port and is memory-mapped into the unified address space.
Four channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead.
The host processor requests the ADSP-2106x’s external bus with
the host bus request (HBR), host bus grant (HBG), and ready
(REDY) signals. The host can directly read and write the inter-
nal memory of the ADSP-2106x, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
Rev. F | Page 5 of 64 | March 2008
5 Page 
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Table 3. Pin Descriptions (Continued)
Pin T
ype Function
ACK
I/O/S
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory
access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The ADSP-2106x deasserts ACK as an output to add waitstates to a synchronous
access of its internal memory. In a multiprocessing system, a slave ADSP-2106x deasserts the bus master’s
ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its
ACK pin that maintains the input at the level to which it was last driven.
SBTS
I/S Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, data,
selects, and strobes in a high impedance state for the following cycle. If the ADSP-2106x attempts to access
external memory while SBTS isasserted, the processor willhalt and the memory access willnot be completed
until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-2106x deadlock,
or used with a DRAM controller.
IRQ2–0
I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.
FLAG3–0
I/O/A
Flag Pins. Each is configured via control bits as either an input or output. As an input, they can be tested as
a condition. As an output, they can be used to signal external peripherals.
TIMEXP O Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero.
HBR I/A Host Bus Request. This pin must be asserted by a host processor to request control of the ADSP-2106x’s
external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus master will
relinquish the bus and assert HBG. To relinquish the bus, the ADSP-2106x places the address, data, select
and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus requests BR6–1 in a
multiprocessing system.
HBG I/O Host Bus Grant. Acknowledges a bus request, indicating that the host processor may take control of the
external bus. HBG is asserted (held low) by the ADSP-2106x until HBR is released. In a multiprocessingsystem,
HBG is output by the ADSP-2106x bus master and is monitored by all others.
CS I/A Chip Select. Asserted by host processor to select the ADSP-2106x.
REDY
O (O/D)
Host BusAcknowledge. The ADSP-2106x deasserts REDY (low) to add wait statesto an asynchronous access
of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be
programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if
the CS and HBR inputs are asserted.
DMAR2–1
I/A
DMA Request 1 (DMA Channel 7) and DMA Request 2 (DMA Channel 8).
DMAG2–1
O/T
DMA Grant 1 (DMA Channel 7) and DMA Grant 2 (DMA Channel 8).
BR6–1
I/O/S
Multiprocessing Bus Requests. Used by multiprocessing ADSP-2106xs to arbitrate for bus master-ship. An
ADSP-2106x only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all
others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins should be pulled
high; the processor’s own BRx line must not be pulled high or low because it is an output.
ID2–0
O (O/D)
Multiprocessing ID. Determines which multiprocessing bus request (BR1– BR6) is used by ADSP-2106x.
ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor systems. These
lines are a system configuration selection that should be hardwired or changed at reset only.
RPBA
I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration
selection that must be set to the same value on every ADSP-2106x. If the value of RPBA is changed during
system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.
CPA I/O (O/D) Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-2106x bus slave to interrupt
background DMA transfers and gain access to the external bus. CPA is an open drain output taht is connected
to all ADSP-2106xs in the system. The CPA pin has an internal 5 k: pull-up resistor. If core access priority is
not required in a system, the CPA pin should be left unconnected.
DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k: internal pull-up resistor.
DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k: internal pull-up resistor.
TCLKx
I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k: internal pull-up resistor.
RCLKx
I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k: internal pull-up resistor.
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)
Rev. F | Page 11 of 64 | March 2008
11 Page | ||
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