24C04A Datasheet PDF - MicrochipTechnology
| Part Number | 24C04A | |
| Description | 1K/2K/4K 5.0V I2C Serial EEPROMs | |
| Manufacturers | MicrochipTechnology | |
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24C04A
4K 5.0V I2C™ Serial EEPROM
FEATURES
• Low power CMOS technology
• Hardware write protect
• Two wire serial interface bus, I2C™ compatible
• 5.0V only operation
• Self-timed write cycle (including auto-erase)
• Page-write buffer
• 1 ms write cycle time for single byte
• 1,000,000 Erase/Write cycles guaranteed
• Data retention >200 years
• 8-pin DIP/SOIC packages
• Available for extended temperature ranges
- Commercial (C):
- Industrial (I):
- Automotive (E):
0˚C to +70˚C
-40˚C to +85˚C
-40˚C to +125˚C
DESCRIPTION
The Microchip Technology Inc. 24C04A is a 4K bit
Electrically Erasable PROM. The device is organized
as with a standard two wire serial interface. Advanced
CMOS technology allows a significant reduction in
power over NMOS serial devices. A special feature
provides hardware write protection for the upper half of
the block. The 24C04A has a page write capability of
up to eight bytes, and up to four 24C04A devices may
be connected to the same two wire bus.
This device offers fast (1ms) byte write and
extended (-40°C to 125°C) temperature operation.
It is recommended that all other applications use
Microchip’s 24LC04B.
PACKAGE TYPES
DIP A0 1
A1 2
A2 3
VSS 4
8-lead
SOIC A0
A1
A2
VSS
14-lead
SOIC
NC
A0
A1
NC
A2
Vss
NC
1
2
3
4
1
2
3
4
5
6
7
8 VCC
7 WP
6 SCL
5 SDA
8 VCC
7 WP
6 SCL
5 SDA
14 NC
13 Vcc
12 WP
11 NC
10 SCL
9 SDA
8 NC
I2C is a trademark of Philips Corporation.
© 1998 Microchip Technology Inc.
BLOCK DIAGRAM
Vcc
Vss
SDA
SCL
Data
Buffer
(FIFO)
Data Reg.
Slave Addr.
Control
Logic
A0 A1 A2 WP
VPP R/W Amp
AP
do
di
rn
et
se
A0 to
A7
sr
Memory
Array
Increment
A8
DS11183E-page 1
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4.0 SLAVE ADDRESS
The chip address inputs A1 and A2 must be externally
connected to either VCC or ground (VSS), thereby
assigning a unique address to each device. A0 is not
used on the 24C04A and must be connected to either
VCC or VSS. Up to four 24C04A devices may be con-
nected to the bus. Chip selection is then accomplished
through software by setting the bits A1 and A2 of the
slave address to the corresponding hard-wired logic lev-
els of the selected 24C04A. After generating a START
condition, the bus master transmits the slave address
consisting of a 4-bit device code (1010), followed by the
chip address bits A0, A1 and A2. The seventh bit of that
byte (A0) is used to select the upper block (addresses
100—1FF) or the lower block (addresses 000—0FF) of
the array.
The eighth bit of the slave address determines if the
master device wants to read or write to the 24C04A
(Figure 4-1).
The 24C04A monitors the bus for its corresponding
slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
FIGURE 4-1: SLAVE ADDRESS
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W A
24C04A
5.0 BYTE PROGRAM MODE
In this mode, the master sends addresses and one
data byte to the 24C04A.
Following the START signal from the master, the device
code (4-bits), the slave address (3-bits), and the R/W
bit, which is logic LOW, are placed onto the bus by the
master. This indicates to the addressed 24C04A that a
byte with a word address will follow after it has gener-
ated an acknowledge bit. Therefore the next byte trans-
mitted by the master is the word address and will be
written into the address pointer of the 24C04A. After
receiving the acknowledge, the master device trans-
mits the data word to be written into the addressed
memory location. The 24C04A acknowledges again
and the master generates a STOP condition. This ini-
tiates the internal programming cycle (Figure 6-1).
1 0 1 0 A2 A1 A0
© 1998 Microchip Technology Inc.
DS11183E-page 5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 24C04A electronic component. |
| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 24C04A.PDF Datasheet ] | |
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