|
|
PDF 24C02B Data sheet ( Hoja de datos )
| Número de pieza | 24C02B | |
| Descripción | 1K/2K 5.0V I2C Serial EEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 24C02B (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
Obsolete Device
Please use 24LC01B or 24LC02B.
24C01B/02B
1K/2K 5.0V I2C™ Serial EEPROM
FEATURES
• Single supply with 5.0V operation
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.0V
- 5 µA standby current typical at 5.0V
• Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8)
• 2-wire serial interface bus, I2C compatible
• 100 kHz compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• ESD protection > 3,000V
• 1,000,000 ERASE/WRITE cycles guaranteed
Data retention > 200 years
• 8 pin DIP or SOIC package
• Available for extended temperature ranges
- Automotive (E):
-40°C to +125°C
DESCRIPTION
The Microchip Technology Inc. 24C01B and 24C02B
are 1K bit and 2K bit Electrically Erasable PROMs. The
devices are organized as a single block of 128 x 8 bit
or 256 x 8 bit memory with a 2-wire serial interface.
The 24C01B and 24C02B also have page-write capa-
bility for up to 8 bytes of data. The 24C01B and 24C02B
are available in the standard 8-pin DIP and an 8-pin
surface mount SOIC package.
These devices are for extended temperature
applications only. It is recommended that all other
applications use Microchip’s 24LC01B/02B.
PACKAGE TYPES
PDIP
NC 1
NC 2
NC 3
Vss 4
8 Vcc
7 WP
6 SCL
5 SDA
SOIC
NC
NC
NC
Vss
1
2
3
4
8 Vcc
7 WP
6 SCL
5 SDA
BLOCK DIAGRAM
WP
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
SDA SCL
VCC
VSS
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
2004 Microchip Technology Inc.
Preliminary
DS21233B-page 1
1 page  
24C01B/02B
3.6 Device Address
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C01B/02B, followed by three
don't care bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24C01B/02B
(Figure 3-2).
The 24C01B/02B monitors the bus for its correspond-
ing slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
Operation
Read
Write
Control
Code
1010
1010
Chip
Select
XXX
XXX
R/W
1
0
FIGURE 3-2: CONTROL BYTE
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W A
1 010XXX
X = Don’t care
FIGURE 4-1:
BUS ACTIVITY
MASTER
BYTE WRITE
S
T CONTROL
A BYTE
R
T
SDA LINE
S
BUS ACTIVITY
A
C
K
4.0 WRITE OPERATION
4.1 Byte Write
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W bit
which is a logic low is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver that a byte with a word address will follow after
it has generated an acknowledge bit during the ninth
clock cycle. Therefore the next byte transmitted by the
master is the word address and will be written into the
address pointer of the 24C01B/02B. After receiving
another acknowledge signal from the 24C01B/02B the
master device will transmit the data word to be written
into the addressed memory location. The 24C01B/02B
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and
during this time the 24C01B/02B will not generate
acknowledge signals (Figure 4-1).
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24C01B/02B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to eight data bytes to
the 24C01B/02B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con-
stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
WORD
ADDRESS
A
C
K
DATA
S
T
O
P
P
A
C
K
FIGURE 4-2: PAGE WRITE
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
S
CONTROL
BYTE
BUS ACTIVITY
WORD
ADDRESS (n)
AA
CC
KK
DATA n
DATAn + 1
DATAn + 7
S
T
O
P
P
AAA
CCC
KKK
2004 Microchip Technology Inc.
Preliminary
DS21233B-page 5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 24C02B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 24c02 | SERIAL 2K(256 x 8) EEPROM |  STMicroelectronics |
| 24C02 | 1K/2K 5.0V I2C Serial EEPROMs | MicrochipTechnology |
| 24C02 | (24C01 - 24C16) 2-WIRE SERIAL CMOS EEPROM |  ISSI |
| 24C02 | 2-Wire Serial EEPROM |  ATMEL Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |