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PDF 2N5192G Data sheet ( Hoja de datos )

Número de pieza 2N5192G
Descripción Silicon NPN Power Transistors
Fabricantes ON Semiconductor 
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2N5190G, 2N5191G,
2N5192G
Silicon NPN Power
Transistors
Silicon NPN power transistors are for use in power amplifier and
switching circuits, − excellent safe area limits. Complement to PNP
2N5194, 2N5195.
Features
Epoxy Meets UL 94 V−0 @ 0.125 in.
These Devices are Pb−Free and are RoHS Compliant*
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Collector−Emitter Voltage
2N5190G
2N5191G
2N5192G
VCEO
40
60
80
Vdc
Collector−Base Voltage
2N5190G
2N5191G
2N5192G
VCBO
40
60
80
Vdc
Emitter−Base Voltage
Collector Current
Base Current
Total Device Dissipation
@ TC = 25°C
Derate above 25°C
VEBO
IC
IB
PD
5.0 Vdc
4.0 Adc
1.0 Adc
40 W
320 mW/°C
Operating and Storage Junction
Temperature Range
TJ, Tstg – 65 to + 150
°C
ESD − Human Body Model
HBM
3B
V
ESD − Machine Model
MM C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction−to−Case
Symbol
RqJC
Max
3.12
Unit
°C/W
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2013
October, 2013 − Rev. 14
1
http://onsemi.com
4.0 AMPERES
NPN SILICON
POWER TRANSISTORS
40, 60, 80 VOLTS − 40 WATTS
COLLECTOR
2
3
BASE
1
EMITTER
TO−225
CASE 77
STYLE 1
123
MARKING DIAGRAM
YWW
2
N519xG
Y = Y ear
WW = W ork Week
2N519x = Device Code
x = 0, 1, or 2
G = Pb−Free Package
ORDERING INFORMATION
Device
2N5190G
2N5191G
2N5192G
Package
TO−225
(Pb−Free)
TO−225
(Pb−Free)
TO−225
(Pb−Free)
Shipping
500 Units/Box
500 Units/Box
500 Units/Box
Publication Order Number:
2N5191/D
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2N5192G pdf
2N5190G, 2N5191G, 2N5192G
10
5.0
TJ = 150°C
2.0
5.0 ms
100 ms
1.0 ms
dc
1.0
SECONDARY BREAKDOWN LIMIT
0.5 THERMAL LIMIT AT TC = 25°C
BONDING WIRE LIMIT
CURVES APPLY BELOW RATED VCEO
0.2 2N5191
0.1
1.0
2.0
2N5192
5.0 10 20
50
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 11. Rating and Thermal Data
Active−Region Safe Operating Area
100
There are two limitations on the power handling ability of
a transistor; average junction temperature and second
breakdown. Safe operating area curves indicate I C − V CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 11 is based on T J(pk) = 150_C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T J(pk)
150_C. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
the limitations imposed by second breakdown.
1.0
0.7 D = 0.5
0.5
0.3 0.2
0.2
0.1
0.1 0.05
0.07
0.05 0.02
0.03 0.01
SINGLE PULSE
0.02
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10
t, TIME OR PULSE WIDTH (ms)
20
Figure 12. Thermal Response
qJC(max) = 3.12°C/W — 2N5190-92
50 100 200
500 1000
DESIGN NOTE: USE OF TRANSIENT THERMAL RESISTANCE DATA
tP
PP
PP
t1
1/f
Figure A
DUTY CYCLE, D = t1 f -
t1
tP
PEAK PULSE POWER = PP
A train of periodical power pulses can be represented by
the model shown in Figure A. Using the model and the
device thermal response, the normalized effective transient
thermal resistance of Figure 12 was calculated for various
duty cycles.
To find qJC(t), multiply thevalue obtained from Figure 12
by the steady state value qJC.
Example:
The 2N5190 is dissipating 50 watts under the following
conditions: t1 = 0.1 ms, tp = 0.5 ms. (D = 0.2).
Using Figure 12, at a pulse width of 0.1 ms and D = 0.2,
the reading of r(t1, D) is 0.27.
The peak rise in function temperature is therefore:
DT = r(t) × PP × qJC = 0.27 × 50 × 3.12 = 42.2_C
http://onsemi.com
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