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PDF FSDM1265RB Data sheet ( Hoja de datos )

Número de pieza FSDM1265RB
Descripción Green Mode Fairchild Power Switch
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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www.fairchildsemi.com
FSDM1265RB
Green Mode Fairchild Power Switch (FPSTM)
Features
• Internal Avalanche Rugged Sense FET
• Advanced Burst-Mode operation that consumes less than
1 W at 240VAC and 0.5W load
• Precision Fixed Operating Frequency (66kHz)
• Internal Start-up Circuit
• Improved Pulse by Pulse Current Limiting
• Over-Voltage Protection (OVP)
• Over-Load Protection (OLP)
• Internal Thermal Shutdown Function (TSD)
• Auto-Restart Mode
• Under Voltage Lock Out (UVLO) with Hysteresis
• Low Operating Current (2.5mA)
• Built-in Soft Start
Application
• SMPS (Switch Mode Power Supplies) for LCD monitor
and STB
• Adapter
OUTPUT POWER TABLE(4)
230VAC ±15%(3)
85-265VAC
PRODUCT
Adapt- Open Adapt- Open
er(1) Frame(2) er(1) Frame(2)
FSDM0565RB 60W
70W
50W
60W
FSDM0565RBI 60W
70W
50W
60W
FSDM07652RB 70W
80W
60W
70W
FSDM1265RB 90W
110W
80W
90W
Table 1. Maximum Output Power
Notes:
1. Typical co ntinuous power in a non-ventilated en closed
adapter measured at 50°C ambient.
2. Maximum pr actical co ntinuous power in an open- fr ame
design at 50°C ambient.
3. 230 VAC or 100/115 VAC with doubler.
4. The junction Temperature can limit the Maximum output power.
Description
The FSDM1265RB is an integrated Pulse-Width Modulator
(PWM) and a SenseFET which is specifically designed for
high performance offline SMPS with minimal external
components. This device is an integrated high-voltage power
switching regulator which combines a rugged avalanche
Sense FET with a current mode PWM control block. The
PWM controller includes integrated fixed frequency oscillator,
under-voltage lockout, leading edge blanking (LEB),optimized
gate driver, internal soft-start, and precise current sources that
are temperature compensated for loop compensation and self
protection circuitry. Compared with discrete MOSFET and
PWM controller solution, it can reduce total cost, component
count, size, and weight, while simultaneously increasing
efficiency, productivity, and system reliability. This device is a
basic platform which is well suited for cost effective designs
of flyback converters.
Typical Circuit
AC
IN
Vstr Drain
PWM
Vfb Vcc Source
Figure 1. Typical Flyback Application
DC
OUT
FPSTM is a trademark of Fairchild Semiconductor Corporation.
©2005 Fairchild Semiconductor Corporation
Rev.1.0.0
http://www.Datasheet4U.com

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FSDM1265RB pdf
Electrical Characteristics
(Ta = 25°C unless otherwise specified)
Parameter S
Sense FET SECTION
Drain-source breakdown voltage
Zero gate voltage drain current
Static drain source on resistance
Output capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
CONTROL SECTION
Initial frequency
Voltage stability
Temperature stability (1)
Maximum duty cycle
Minimum duty cycle
Start threshold voltage
Stop threshold voltage
Feedback source current
Soft-start time
Leading edge blanking time
BURST MODE SECTION
Burst mode voltages(1)
FSDM1265RB
ymbol
Condition
Min. Typ. Max. Unit
BVDSS
IDSS
RDS(ON)
VGS = 0V, ID = 250µA
VDS = 650V, VGS = 0V
VDS= 520V
VGS = 0V, TC = 125°C
VGS = 10V, ID = 2.5A
COSS
VGS = 0V, VDS = 25V,
f = 1MHz
TD(ON)
TR
TD(OFF)
TF
VDD= 325V, ID= 5A
650 -
-
- - 500
- - 500
- 0.75 0.9
-7 8 -
-4 2
- 106
- 330
-1 10
-
-
-
-
V
µA
µA
pF
ns
FOSC
FSTABLE
FOSC
DMAX
DMIN
VSTART
VSTOP
IFB
TS
TLEB
VFB = 3V
13V Vcc 18V
-25°C Ta 85°C0
-7
--
VFB=GND
VFB=GND
VFB=GND
Vfb=3
-
60 66 72 kHz
0 1 3%
±5± 10 %
7 82 87 %
- 0%
11 12 13 V
78 9V
0.7 0.9 1.1 mA
- 10 15 ms
- 250 -
ns
VBURH
VBURL
Vcc=14V
Vcc=14V
0.3 0.38 0.46
0.39 0.49 0.59
V
V
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FSDM1265RB arduino
FSDM1265RB
Functional Description
1. Star-tup: In p revious g enerations o f Fairchild Power
Switches ( FPSTM), the Vcc p in h ad an ex ternal start- up to
the DC input voltage line. In the newer switches, the startup
resistor is replaced b y an internal h igh v oltage current
source. At startu p, an in ternal h igh v oltage c urrent so urce
supplies the internal bias and charges the external capacitor
(Cvcc) th at is co nnected to th e Vcc p in a s illu strated in
Figure 4. When the Vcc pin reaches 12V, the FSDM1265RB
begins switching and the internal high voltage current source
is di sabled. Th en, t he F SDM1265RB c ontinues its no rmal
switching o peration an d th e p ower is s upplied from th e
auxiliary transformer win ding unless Vcc g oes b elow th e
stop voltage of 8V.
CVcc
VDC
2.1 Pulse-by-pulse curr ent limit : B ecause cu rrent m ode
control is employed, the peak current through the Sense-FET
is limited by the inverting input of PWM comparator (Vfb*)
as sh own i n F igure 5. A ssuming that t he 0.9mA c urrent
source flows only through the internal resistor (2.5R +R= 2.8
k), the cathode voltage of diode D2 is about 2.5V. Since D1
is blocked when th e feed back v oltage (Vf b) ex ceeds 2.5V,
the maximum voltage of the cathode of D2 is clamped at this
voltage, t hus c lamping V fb*. Therefore, the peak va lue o f
the current through the Sense FET is limited.
2.2 Leading edge blanking (LEB): When the internal Sense
FET is tu rned o n, u sually th e rev erse reco very of th e
primary-side cap acitance and th e seco ndary-side r ectifier
causes a h igh current sp ike th rough th e Sen seFET. ca uses
Excessive voltage acr oss th e R sense resistor can lead to
incorrect fee dback operation in th e cu rrent m ode PW M
control. To counter this effect, the FSDM1265RB employs a
leading edge blanking (LEB) circuit. This circuit inhibits the
PWM co mparator fo r a short tim e ( TLEB) afte r th e
SenseFET is turned on.
Vcc
3
8V/12V
Vcc good
6 Vstr
Istart
Vref
Internal
Bias
Figure 4. Internal startup circuit
Vcc Vref
Idelay
IFB
Vo Vfb
H11A817A
4
CB
OSC
D1 D2
2.5R
KA431
+
Vfb* R
-
SenseFET
Gate
driver
VSD
OLP
Rsense
Figure 5. Pulse width modulation (PWM) circuit
2. Feedback Control: FSDM1265RB employs current mode
control, as shown in Figure 5. An opto-coupler (such as the
H11A817A) a nd s hunt re gulator (s uch a s t he K A431) a re
typically u sed to im plement th e feed back n etwork.
Comparing the feedback voltage with the voltage across the
Rsense resistor in addition to the offset voltage makes it possible
to control the switching duty cycle. When the reference pin voltage
of th e K A431 e xceeds the inte rnal re ference vo ltage of 2.5 V, the
H11A817A L ED c urrent i ncreases, t hereby p ulling down t he
feedback vo ltage an d reducing t he duty cy cle. T ypically t his
happens wh en the in put v oltage is in creased or th e o utput
load is decreased.
3. Pr otection Ci rcuit: The F SDM1265RB ha s s everal se lf
protective functions su ch as ove rload pro tection (O LP), ove r
voltage pr otection (O VP) an d t hermal sh utdown (T SD). Be cause
these pro tection cir cuits ar e fu lly in tegrated into the IC w ithout
external co mponents, th e rel iability ca n be im proved w ithout
increasing c ost. Once t he fault c ondition o ccurs, switching is
terminated and the SenseFET remains off. This causes Vcc to fall.
When Vcc reaches the UV LO stop voltage (8V), the protection is
reset and the internal hig h voltage cu rrent so urce charges the V cc
capacitor via the Vstr pin. W hen the Vcc re aches the UV LO start
voltage (12 V ), th e F SDM1265RB r esumes i ts n ormal op eration.
Thus, the auto-restart alternately enables and disables the switching
of the power SenseFET until th e fa ult co ndition is elim inated
(see Figure 6).
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