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ON Semiconductor - Ultra-Low Jitter Low Skew 1:12 LVCMOS - LVTTL Fanout Buffer

Numéro de référence NB3V8312C
Description Ultra-Low Jitter Low Skew 1:12 LVCMOS - LVTTL Fanout Buffer
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NB3V8312C fiche technique
NB3V8312C
Ultra-Low Jitter, Low Skew
1:12 LVCMOS/LVTTL Fanout
Buffer
The NB3V8312C is a high performance, low skew L VCMOS
fanout buffer which can distribute 12 ultra low jitter clocks from an
LVCMOS/LVTTL input up to 250 MHz.
http://onsemi.com
The 12 LVCMOS output pins drive 50 W series or parallel
terminated transmission lines. The outputs can also be disabled to a
high impedance (tristated) via the OE input, or enabled when High.
The NB3V8312C provides an enable input, CLK_EN pin, which
synchronously enables or disables the clock outputs while in the LOW
state. Since this input is internally synchronized to the input clock,
changing only when the input is LOW , potential output glitching or
runt pulse generation is eliminated.
LQFP32
FA SUFFIX
CASE 873A
1 32
QFN32
MN SUFFIX
CASE 488AM
Separate V DD core and V DDO output supplies allow the output
buffers to operate at the same supply as the V DD (VDD = V DDO) or
from a lower supply voltage. Compared to single supply operation,
VDDO
VDD
GND
Q0
dual supply operation enables lower power consumption and
outputlevel compatibility.
The VDD core supply voltage can be set to 3.3 V , 2.5 V or 1.8 V,
while the VDDO output supply voltage can be set to 3.3 V , 2.5 V, or
1.8 V, with the constraint that VDD VDDO.
This buffer is ideally suited for various networking, telecom, server
CLK_EN
RPU
D
Q
Q1
Q2
Q3
Q4
and storage area networking, RRU LO reference distribution, medical
and test equipment applications.
Features
Power Supply Modes:
CLK
RPD
Q5
Q6
Q7
VDD (Core) / VDDO (Outputs)
3.3 V
/ 3.3 V
3.3 V
/ 2.5 V
3.3 V
/ 1.8 V
Q8
Q9
Q10
2.5 V
2.5 V
1.8 V
/ 2.5 V
/ 1.8 V
/ 1.8 V
RPU
OE
Q11
250 MHz Maximum Clock Frequency
Figure 1. Simplified Logic Diagram
Accepts LVCMOS, LVTTL Clock Inputs
LVCMOS Compatible Control Inputs
12 LVCMOS Clock Outputs
Synchronous Clock Enable
ORDERING AND MARKING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
Output Enable to High Z State Control
150 ps Max. Skew Between Outputs
Temp. Range 40°C to +85°C
32pin LQFP and QFN Packages
Applications
Networking
Telecom
Storage Area Network
These are PbFree Devices
End Products
Servers
Routers
Switches
© Semiconductor Components Industries, LLC, 2013
August, 2013 Rev. 0
1
Publication Order Number:
NB3V8312C/D
http://www.Datasheet4U.com

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