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PDF NB3N51034 Data sheet ( Hoja de datos )
| Número de pieza | NB3N51034 | |
| Descripción | 3.3V Crystal to 100MHz - 200MHz Quad HCSL - LVDS Clock Generator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB3N51034
3.3V, Crystal to 100MHz/
200MHz Quad HCSL/LVDS
Clock Generator
The NB3N51034 is a high precision, low phase noise clock generator
that supports spread spectrum designed for PCI Express applications.
This device takes a 25 MHz fundamental mode parallel resonant crystal
and generates 4 dif ferential HCSL/L VDS outputs at 100 MHz or
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200 MHz (See Figure 6 for LVDS interface). The NB3N51034 provides
selectable spread options of −0.5%, −1.0%, −1.5%, for applications
demanding low Electromagnetic Interference (EMI). No spread setting
MARKING
DIAGRAM
is also available.
Features
• Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
• Power Down Mode
• 4 Low Skew HCSL or LVDS Outputs
TSSOP−20
DT SUFFIX
CASE 948E
NB3N
1034
ALYWG
G
• OE Tri−States Outputs
• Spread of −0.5%, −1.0%, −1.5% and No Spread
• PCIe Gen 1, 2, 3 Jitter Compliant
• Phase Noise (SS OFF) @ 100 MHz:
Offset Noise Power
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
100 Hz
1 kHz
10 kHz
100 kHz
−110 dBc/Hz
−123 dBc/Hz
−134 dBc/Hz
−137 dBc/Hz
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
1 MHz −138 dBc/Hz
10 MHz −154 dBc/Hz
• Operating Range 3.3 V ±5%
• Computing and Peripherals
• Industrial Temperature Range −40°C to +85°C
• Industrial Equipment
• Functionally Compatible with IDT557−05,
• PCIe Clock Generation Gen I, Gen II and Gen III
IDT5V41066, IDT5V41236
• These are Pb−Free Devices
End Products
• Switch and Router
Applications
• Networking
• Consumer
• Set Top Box, LCD TV
• Servers, Desktop Computers
• Automated Test Equipment
VDD
S0 S1 S2
PD OE
X1/CLK
25 MHz Clock
or Crystal X2
Clock Buffer
Crystal Oscillator
Spread Spectrum
Circuit
Phase
Detector
BN
Charge
Pump
VCO
HCSL
Output
HCSL
Output
HCSL
Output
HCSL
Output
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
GND Figure 1. NB3N51034 Simplified Logic Diagram
IREF
© Semiconductor Components Industries, LLC, 2013
October, 2013 − Rev. 1
1
Publication Order Number:
NB3N51034/D
http://www.Datasheet4U.com
1 page  
NB3N51034
Table 7. AC ELECTRICAL CHARACTERISTICS − PCI EXPRESS JITTER SPECIFICATIONS,
VDD = 3.3 V ± 5%, TA = −40°C to 85°C
Symbol
Parameter
Test Conditions
Min Typ Max
PCIe
Industry
Spec
Unit
tj (PCIe Gen 1)
Phase Jitter
Peak−to−Peak
(Notes 16
and 19)
f = 100 MHz, 25 MHz Crystal
Input Evaluation Band:
0 Hz − Nyquist (clock
frequency/2)
SSOFF
SSON
(−0.5%)
10 20 86 ps
19 28
tREFCLK_HF_RMS
(PCIe Gen 2)
Phase Jitter
RMS (Notes 17
and 19)
f = 100 MHz, 25 MHz Crystal
Input High Band:
1.5 MHz − Nyquist (clock
frequency/2)
SSOFF
SSON
(−0.5%)
1.0 1.8 3.1 ps
1.1 1.9
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter
RMS (Notes 17
and 19)
f = 100 MHz, 25 MHz Crystal
Input Low Band:
10 kHz − 1.5 MHz
SSOFF
SSON
(−0.5%)
0.1 0.15
0.8 1.1
3.0
ps
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter
RMS (Notes 18
and 19)
f = 100 MHz, 25 MHz Crystal
Input Evaluation Band: 0 Hz −
Nyquist (clock frequency/2)
SSOFF
SSON
(−0.5%)
0.35 0.7 1.0 ps
0.55 0.8
15. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the d evice is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal
equilibrium has been reached under these conditions.
16. Peak−to−Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86 ps
peak−to−peak for a sample size of 106 clock periods.
17. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the
worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1 ps RMS for tREFCLK_HF_RMS (High Band)
and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
18. RMS jitter after applying system transfer function for the common clock architecture.
19. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W, RL = 50 W, with test load capacitance
of 2 pF and current biasing resistor set at 475 W. See Figure 5. This parameter is guaranteed by characterization. Not tested in production.
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