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PDF 74LVC8T245 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC8T245 | |
| Descripción | 8-bit dual supply translating transceiver | |
| Fabricantes | NXP Semiconductors | |
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74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
Rev. 3 — 12 December 2011
Product data sheet
1. General description
The 74LVC8T245; 74LVCH8T245 are 8-bit dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two data
input-output ports (pins An and Bn), a direction control input (DIR), an output enable input
(OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at
any voltage between 1.2 V and 5.5 V making the device suitable for translating between
any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and
DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows
transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The
output enable input (OE) can be used to disable the outputs so the buses are effectively
isolated.
The devices are fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a
valid logic level.
2. Features and benefits
Wide supply voltage range:
VCC(A): 1.2 V to 5.5 V
VCC(B): 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
http://www.Datasheet4U.com
1 page  
NXP Semiconductors
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
IGND
Tstg
Ptot
ground current
storage temperature
total power dissipation
per GND pin
Tamb = 40 C to +125 C
100
65
[4] -
-
+150
500
mA
C
mW
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 6.5 V.
[4] For TSSOP24 package: Ptot derates linearly at 5.5 mW/K above 60 C.
For DHVQFN24 package: Ptot derates linearly at 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Symbol
VCC(A)
VCC(B)
VI
VO
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage A
supply voltage B
input voltage
output voltage
Active mode
Suspend or 3-state mode
ambient temperature
input transition rise and fall rate
VCCI = 1.2 V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3 V to 3.6 V
VCCI = 4.5 V to 5.5 V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
9. S tatic characteristics
Min
1.2
1.2
0
[1] 0
0
40
[2] -
-
-
-
-
Max
5.5
5.5
5.5
VCCO
5.5
+125
20
20
20
10
5
Unit
V
V
V
V
V
C
ns/V
ns/V
ns/V
ns/V
ns/V
Table 6. Typical static characteristics at Tamb = 25 C
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VOH HIGH-level output voltage VI = VIH or VIL
IO = 3 mA; VCCO = 1.2 V
VOL LOW-level output voltage VI = VIH or VIL
IO = 3 mA; VCCO = 1.2 V
II
input leakage current
DIR, OE input; VI = 0 V to 5.5 V;
VCCI = 1.2 V to 5.5 V
IBHL bus hold LOW current
A or B port; VI = 0.42 V; VCCI = 1.2 V
IBHH bus hold HIGH current A or B port; VI = 0.78 V; VCCI = 1.2 V
Min
[1]
-
[1] -
[2] -
[2] -
[2] -
Typ
1.09
0.07
-
19
19
Max Unit
-V
-V
1 A
- A
- A
74LVC_LVCH8T245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
5 of 28
5 Page 
NXP Semiconductors
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
Table 11. Dynamic characteristics for temperature range 40 C to +85 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.5 V 0.1 V
tpd propagation
delay
An to Bn
Bn to An
1.7 27 1.7 23 1.3 18 1.0 15 0.8 13 ns
0.9 27 0.9 25 0.8 23 0.7 23 0.7 22 ns
tdis disable time OE to An
OE to Bn
1.5 30 1.5 30 1.5 30 1.5 30 1.4 30 ns
2.4 34 2.4 33 1.9 15 1.7 14 1.3 12 ns
ten
enable time
OE to An
OE to Bn
0.4 34 0.4 34 0.4 34 0.4 34 0.4 34 ns
1.8 36 1.8 34 1.5 18 1.2 15 0.9 13 ns
VCC(A) = 1.8 V 0.15 V
tpd propagation
delay
An to Bn
Bn to An
1.7 25 1.7 21.9 1.3 9.2 1.0 7.4 0.8 7.1 ns
0.9 23 0.9 23.8 0.8 23.6 0.7 23.4 0.7 23.4 ns
tdis disable time OE to An
OE to Bn
1.5 30 1.5 29.6 1.5 29.4 1.5 29.3 1.4 29.2 ns
2.4 33 2.4 32.2 1.9 13.1 1.7 12.0 1.3 10.3 ns
ten
enable time
OE to An
OE to Bn
0.4 24 0.4 24.0 0.4 23.8 0.4 23.7 0.4 23.7 ns
1.8 34 1.8 32.0 1.5 16.0 1.2 12.6 0.9 10.8 ns
VCC(A) = 2.5 V 0.2 V
tpd propagation
delay
An to Bn
Bn to An
1.5 23 1.5 21.4 1.2 9.0 0.8 6.2 0.6 4.8 ns
1.2 18 1.2 9.3 1.0 9.1 1.0 8.9 0.9 8.8 ns
tdis disable time OE to An
OE to Bn
1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 1.4 9.0 ns
2.3 31 2.3 29.6 1.8 11.0 1.7 9.3 0.9 6.9 ns
ten
enable time
OE to An
OE to Bn
1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 1.0 10.9 ns
1.7 32 1.7 28.2 1.5 12.9 1.2 9.4 1.0 6.9 ns
VCC(A) = 3.3 V 0.3 V
tpd propagation
delay
An to Bn
Bn to An
1.5 23 1.5 21.2 1.1 8.8 0.8 6.3 0.5 4.4 ns
0.8 15 0.8 7.2 0.8 6.2 0.7 6.1 0.6 6.0 ns
tdis disable time OE to An
OE to Bn
1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 ns
2.1 30 2.1 29.0 1.7 10.3 1.5 8.6 0.8 6.3 ns
ten
enable time
OE to An
OE to Bn
0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 ns
1.8 31 1.8 27.7 1.4 12.4 1.1 8.5 0.9 6.4 ns
VCC(A) = 5.0 V 0.5 V
tpd propagation
delay
An to Bn
Bn to An
1.5 22 1.5 21.4 1.0 8.8 0.7 6.0 0.4 4.2 ns
0.7 13 0.7 7.0 0.4 4.8 0.3 4.5 0.3 4.3 ns
tdis disable time OE to An
OE to Bn
0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 ns
2.0 30 2.0 28.7 1.6 9.7 1.4 8.0 0.7 5.7 ns
ten
enable time
OE to An
OE to Bn
0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 ns
1.5 31 1.5 27.6 1.3 11.4 1.0 8.1 0.9 6.0 ns
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
74LVC_LVCH8T245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 December 2011
© NXP B.V. 2011. All rights reserved.
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11 Page | ||
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| PDF Descargar | [ Datasheet 74LVC8T245.PDF ] | |
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