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PDF HFC0100 Data sheet ( Hoja de datos )

Número de pieza HFC0100
Descripción QUASI RESONANT CONTROLLER
Fabricantes MPS 
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No Preview Available ! HFC0100 Hoja de datos, Descripción, Manual

The Future of Analog IC Technology
DESCRIPTION
The HFC0100 is a peak current mode controller
with Green Mode Operation. Its high efficiency
feature over the entire line and load range
meets the stringent
world-wide energy
efficiency requirements.
The HFC01 00 integrate d with a high voltage
current sou rce, its valley detector ensures
minimum Drain-Source voltage switching
(Quasi-Resonant oper ation). Whe n the outpu t
power falls below a given level, the controller
enters the burst mode.
The HFC0100 features variable protections like
Thermal Sh utdown (TSD), Vcc Un der voltage
Lockout (UVLO), Over Load Protection (OLP),
Over Voltage Protection (OVP).
The HF C0100 is a vailable in th e 8-p in SOI C8
package.
HFC0100
QUASI RESONANT CONTROLLER
FEATURES
Universal Main Input Voltage (85~265VAC)
Quasi-Resonant Operation
Valley Switching for high efficiency and EMI
Active Burst Mode for low standby powe r
consumption
Internal High Voltage Current Source
High level of integration , allows a very low
number external component count
Maximum Frequency Limited
Internal Soft Start
Internal 250nS Leading Edge Blanking
Thermal shutdown (auto resta
rt with
hysteresis)
Vcc Under Voltage Lockout with Hysteresis
(UVLO)
Over Voltage Protection
Over Load Protection.
APPLICATIONS
Battery ch arger: cellular phone, digital
camera, video camera, electrical shaver,
emergency lighting system, etc
Standby power supply: CRT-TV, Projection-
TV, LCD-TV, PDP-TV, Desk top PC, Audio
system, etc
SMPS: Inc jet printer, DVD player/recorder,
VCR, CD player, Set top
box, Air
conditioner, refrigerator, washing machine,
dish washer, Adapter for NB, etc
For MPS green status, please visit MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
HFC0100 Rev. 1.01
www.MonolithicPower.com
9/23/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
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HFC0100 pdf
HFC0100
QUASI RESONANT CONTROLLER
PIN FUNCTIONS
Pin # Name
1 VSD
2 V cc
3 N/C
4 HV
5 Drive
6 CS
7 GND
8 FB
Description
Input from the auxiliary flyback signal, it ensures discontinuous operation and valley
switching. It also offers a fixed OVP detection.
Supply voltage Pin. This pin is connected to an external bulk capacitor of typically 22uf and a
ceramic capacitor of typically 0.1uF.
This Pin ensures adequate creepage distance.
Input for the start up current unit.
Output of the driving signal.
Input of the current sense.
Ground.
The Pin sets the peak cu rrent limit, by conne cting an optocoupl er to this Pin. A feedback
voltage of 3.7V will trigger an over load protection, and a feedback voltage of 0.5V will trigger
a burst mode operation.
HFC0100 Rev. 1.01
www.MonolithicPower.com
9/23/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
5

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HFC0100 arduino
HFC0100
QUASI RESONANT CONTROLLER
Burst Operation
To minimize the power dissipat ion in no load or
light load, the HFC010 0 enters the burst mo de
operation. As the load decreases, th e FB voltage
decreases,, the HFC0100 stops the switching
cycle when the FB voltage drop s below th e
threshold V BURL—0.5V. And the o utput voltage
starts to dr op at a rat e dependen t on the loa d.
This cau ses the FB volt age to rise again. Once
the FB voltage exceeds the threshold VBURH
0.7V, switching resumes. The FB voltage then
falls and rises repeat edly. The burst mode
operation alternately enables and disables
switching cycle of the MOSFET thereby reducing
switching loss in the no load or light lo ad
conditions.
Figure 8 shows the typical F B and Drive
waveform during the burst mode.
Current Limit Setting
The switch current is sensed b y the resistor
series betw een the Source of the FET and th e
ground. And the current limit is determined by the
FB signal,
VLimit
=
VFB
Idiv
=
VFB
3
. To limit the
maximum output power, the current limit is
clamped at 1V when VFB is bigger than 3.3V.
Leading Edge Blanking
In order to avoid the premature termination of the
switching pulse due to the parasitic capacitance,
an internal leading edg e blanking (LEB) unit is
employed b etween the CS Pin and the curre nt
comparator input. During the blanking time, the
path, CS Pi n to the current comparator input, is
blocked. Figure 9 shows the leading edge
blanking.
VBURH:0.7V
VLimit
VBURL:0.5V
VFB
200mV/div
VDrive
5V/div
40us/div
Figure 8—Burst Mode
Thermal Shutdown (TSD)
To prevents from any lethal thermal damage. The
HFC0100 shuts down switching cycle when th e
inner temperature exceeds 150DegC. As soon as
the inner temperature drops below 100DegC, the
power supply resumes operation.
Soft-Start
To reduce t he stress o n primary MOSFET and
secondary diode durin g start up, to smoothly
establish th e output voltage, the H FC0100 has
an internal soft-start circuit that increases t he
current co mparator inverting input voltage,
together with the MOSF ET current, slowly after it
starts up. The pulse width to the power switching
device is progressively increased to establish the
correct wo rking cond itions for t ransformers,
inductors, and capacitors.
TLEB = 250 nS
t
Figure 9—Leading Edge Blanking
Over Power Compensation
In the case of current sensing, sh ows as figure
10, the turn off of the F ET is delayed due to the
propagation delay of the control cir cuit, the dela y
time is the inherent ch aracteristic of the contr ol
circuit, so T delay can be s een fixed. T his delay will
cause an o vershoot of the peak current. I2 is
bigger than I1 due to the bigger rising ratio(th e
higher input voltage, the bigger rising ratio).
HFC0100 Rev. 1.01
www.MonolithicPower.com
9/23/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
11

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