PDF 2096E Data sheet ( Hoja de datos )

Número de pieza	2096E
Descripción	In-SystemProgrammableSuperFASTHighDensityPLD
Fabricantes	LatticeSemiconductor
Logotipo
Hay una vista previa y un enlace de descarga de 2096E (archivo pdf) en la parte inferior de esta página. Total 11 Páginas
No Preview Available ! ispLSI® 2096E In-System Programmable SuperFAST™ High Density PLD Features Functional Block Diagram • SUPERFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional/JEDEC Upward Compatible with ispLSI 2096 Devices Output Routing Pool (ORP) C7 C6 C5 C4 A0 DQ A1 Logic D Q A2 GLB Array D Q DQ A3 A4 A5 A6 A7 Output Routing Pool (ORP) C3 C2 C1 C0 B7 Global Routing Pool (GRP) B6 B5 B4 B0 B1 B2 B3 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 180 MHz Maximum Operating Frequency — tpd = 5.0 ns Propagation Delay — TTL Compatible Inputs and Outputs — 5V Programmable Logic Core — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User-Selectable 3.3V or 5V I/O Supports Mixed- Voltage Systems — PCI Compatible Outputs — Open-Drain Output Option — Electrically Erasable and Reprogrammable — Non-Volatile — Unused Product Term Shutdown Saves Power • ispLSI OFFERS THE FOLLOWING ADDED FEATURES — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Output Routing Pool (ORP) Output Routing Pool (ORP) Description 0919/2096E The ispLSI 2096E is a High Density Programmable Logic Device. The device contains 96 Registers, 96 Universal I/O pins, six Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2096E offers non-volatile reprogrammability of all logic, as well as the interconnect to provide truly reconfigurable sys- tems. The basic unit of logic on the ispLSI 2096E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. C7 (see Figure 1). There are a total of 24 GLBs in the ispLSI 2096E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered.Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The device also has 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi- directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be pro- grammed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com November 1998 2096e_03 1 1 page Specifications ispLSI 2096E External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST COND.4 #2 DESCRIPTION1 -180 -135 -100 UNITS MIN. MAX. MIN. MAX. MIN. MAX. tpd1 A 1 Data Prop Delay, 4PT Bypass, ORP Bypass – 5.0 – 7.5 – 10.0 ns tpd2 A 2 Data Prop Delay – 7.5 – 10.0 – 13.0 ns fmax A 3 Clk Freq with Internal Feedback3 180 – 135 – 100 – MHz fmax (Ext.) fmax (Tog.) – 4 Clk Freq with External Feedback (1 tsu2 + )tco1 – 5 Clk Frequency, Max. Toggle 125 – 100 – 77 – 200 – 143 – 100 – MHz MHz tsu1 – 6 GLB Reg Setup Time before Clk, 4 PT Bypass 4.0 – 5.0 – 6.5 – ns tco1 A 7 GLB Reg Clk to Output Delay, ORP Bypass – 3.0 – 4.0 – 5.0 ns th1 – 8 GLB Reg Hold Time after Clk, 4 PT Bypass 0.0 – 0.0 – 0.0 – ns tsu2 – 9 GLB Reg Setup Time before Clk 5.0 – 6.0 – 8.0 – ns tco2 – 10 GLB Reg Clk to Output Delay – 3.5 – 4.5 – 6.0 ns th2 – 11 GLB Reg Hold Time after Clk 0.0 – 0.0 – 0.0 – ns tr1 A 12 External Reset Pin to Output Delay – 7.0 – 10.0 – 13.5 ns trw1 – 13 External Reset Pulse Duration 4.0 – 5.0 – 6.5 – ns tptoeen B 14 Input to Output Enable – 10.0 – 12.0 – 15.0 ns tptoedis C 15 Input to Output Disable – 10.0 – 12.0 – 15.0 ns tgoeen B 16 Global OE Output Enable – 5.0 – 7.0 – 9.0 ns tgoedis C 17 Global OE Output Disable – 5.0 – 7.0 – 9.0 ns twh – 18 External Synch Clk Pulse Duration, High 2.5 – 3.5 – 5.0 – ns twl – 19 External Synch Clk Pulse Duration, Low 2.5 – 3.5 – 5.0 – ns 1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2-0030A/2096E 5 5 Page Specifications ispLSI 2096E Part Number Description ispLSI 2096E– XXX X XXXX X Device Family Device Number Speed 180 = 180 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax Grade Blank = Commercial Package T128 = TQFP Q128 = PQFP Power L = Low 0212/2096E ispLSI 2096E Ordering Information FAMILY ispLSI fmax (MHz) 180 180 135 135 100 100 tpd (ns) 5.0 5.0 7.5 7.5 10.0 10.0 ORDERING NUMBER ispLSI 2096E-180LT128 ispLSI 2096E-180LQ128 ispLSI 2096E-135LT128 ispLSI 2096E-135LQ128 ispLSI 2096E-100LT128 ispLSI 2096E-100LQ128 PACKAGE 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP Table 2-0041/2096E 11 11 Page

Páginas	Total 11 Páginas
PDF Descargar	[ Datasheet 2096E.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
2096E	In-SystemProgrammableSuperFASTHighDensityPLD	LatticeSemiconductor
2096VE	3.3VIn-SystemProgrammableSuperFASTHighDensityPLD	LatticeSemiconductor
2096VL	2.5VIn-SystemProgrammableSuperFASTHighDensityPLD	LatticeSemiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar