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PDF IRF9640S Data sheet ( Hoja de datos )

Número de pieza IRF9640S
Descripción Power MOSFET ( Transistor )
Fabricantes Vishay 
Logotipo Vishay Logotipo



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No Preview Available ! IRF9640S Hoja de datos, Descripción, Manual

IRF9640S, SiHF9640S, IRF9640L, SiHF9640L
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
Qg (Max.) (nC)
- 200
VGS = - 10 V
44
Qgs (nC)
7.1
Qgd (nC)
27
Configuration
Single
I2PAK (TO-262)
D2PAK (TO-263)
0.50
S
G
DS
G
D
S
G
D
P-Channel MOSFET
FEATURES
Halogen-free According to IEC 61249-2-21
Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• P-Channel
• Fast Switching
• Ease of Paralleling
• Compliant to RoHS Directive 2002/95/EC
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO-263) is a surface mount power package. It
provides the highest power capability and the lowest
possible on-resistance in any existing surface mount
package. The D2PAK (TO-263) is suitable for high current
applications because of its low internal connection
resistance and can dissipate up to 2.0 W in a typical surface
mount application. The through-hole version (IRF9640L,
SiHF9640L) is available for low-profile applications.
ORDERING INFORMATION
Package
D2PAK (TO-263)
Lead (Pb)-free and Halogen-free SiHF9640S-GE3
Lead (Pb)-free
IRF9640SPbF
SiHF9640S-E3
Note
a. See device orientation.
D2PAK (TO-263)
-
IRF9640STRLPbFa
SiHF9640STL-E3a
D2PAK (TO-263)
-
IRF9640STRRPbFa
SiHF9640STR-E3a
I2PAK (TO-262)
SiHF9640L-GE3
IRF9640LPbF
SiHF9640L-E3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Currenta
Linear Derating Factor
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Avalanche Currenta
Repetiitive Avalanche Energya
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
VGS at - 10 V
TC = 25 °C
TC = 100 °C
VDS
VGS
ID
IDM
TC = 25 °C
TA = 25 °C
EAS
IAR
EAR
PD
dV/dt
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
TJ, Tstg
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = - 50 V, starting TJ = 25 °C, L = 8.7 mH, Rg = 25 , IAS = - 11 A (see fig. 12).
c. ISD - 11 A, dI/dt 150 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
LIMIT
- 200
± 20
- 11
- 6.8
- 44
1.0
0.025
700
- 11
13
125
3.0
- 5.0
- 55 to + 150
300d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91087
S11-1052-Rev. D, 30-May-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

1 page




IRF9640S pdf
IRF9640S, SiHF9640S, IRF9640L, SiHF9640L
Vishay Siliconix
12
10
8
6
4
2
0
25
91087_09
50 75 100 125
TC, Case Temperature (°C)
150
Fig. 9 - Maximum Drain Current vs. Case Temperature
10
VDS
VGS
Rg
RD
D.U.T.
- 10 V
Pulse width 1 µs
Duty factor 0.1 %
-
+VDD
Fig. 10a - Switching Time Test Circuit
VGS
10 %
td(on) tr
td(off) tf
90 %
VDS
Fig. 10b - Switching Time Waveforms
1
D = 0.50
0.20
0.1 0.10
0.05
0.02
0.01
10-2
10-5
91087_11
Single Pulse
(Thermal Response)
10-4
10-3
10-2
0.1
t1, Rectangular Pulse Duration (s)
PDM
t1
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
1 10
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
Vary tp to obtain
required IAS
Rg
- 10 V
tp
L
D.U.T
IAS
0.01 Ω
-
+
V
DD
Fig. 12a - Unclamped Inductive Test Circuit
IAS
VDS
VDD
tp
VDS
Fig. 12b - Unclamped Inductive Waveforms
Document Number: 91087
S11-1052-Rev. D, 30-May-11
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

5 Page










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