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PDF ADP2323 Data sheet ( Hoja de datos )
| Número de pieza | ADP2323 | |
| Descripción | 20 V Synchronous Step-Down Regulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Dual 3 A, 20 V Synchronous Step-Down
Regulator with Integrated High-Side MOSFET
ADP2323
FEATURES
Input voltage: 4.5 V to 20 V
±1% output accuracy
Integrated 90 mΩ typical high-side MOSFET
Flexible output configuration
Dual output: 3 A/3 A
Parallel single output: 6 A
Programmable switching frequency: 250 kHz to 1.2 MHz
External synchronization input with programmable phase
shift, or internal clock output
Selectable PWM or PFM mode operation
Adjustable current limit for small inductor
External compensation and soft start
Startup into precharged output
Supported by ADIsimPower™ design tool
APPLICATIONS
Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point of load applications
GENERAL DESCRIPTION
The ADP2323 is a full featured, dual output, step-down dc-to-
dc regulator based on current-mode architecture. The ADP2323
integrates two high-side power MOSFETs and two low-side drivers
for the external N-channel MOSFETs. The two pulse-width mod-
ulation (PWM) channels can be configured to deliver dual 3 A
outputs or a parallel-to-single 6 A output. The regulator operates
from input voltages of 4.5 V to 20 V, and the output voltage can
be as low as 0.6 V.
The switching frequency can be programmed between 250 kHz
and 1.2 MHz, or synchronized to an external clock to minimize
interference in multirail applications. The dual PWM channels
run 180° out of phase, thereby reducing input current ripple as
well as reducing the size of the input capacitor.
The bidirectional synchronization pin can be programmed at
a 60°, 90°, or 120° phase shift, providing the possibility for a
stackable multiphase power solution.
The ADP2323 can be set to operate in pulse-frequency modulation
(PFM) mode at a light load for higher efficiency or in forced
PWM for noise sensitive applications. External compensation
and soft start provide design flexibility. Independent enable
TYPICAL APPLICATION CIRCUIT
RTOP1
RBOT1
CC1
RC1 CSS1
VIN
CIN1
CINT
CDRV
ROSC
INTVCC
MODE
SCFG
TRK2
TRK1
VDRV
GND
PGOOD2
PGOOD1
SYNC
RT
ADP2323
SW1
CBST1
L1
M1
DL1
PGND
DL2
M2
SW2
L2
CBST2
RBOT2
RTOP2
RC2
CC2
CSS2
CIN2
VIN
VOUT1
COUT1
COUT2
VOUT2
Figure 1.
inputs and power good outputs provide reliable power sequencing.
To enhance system reliability, the device also includes undervoltage
lockout (UVLO), overvoltage protection (OVP), overcurrent pro-
tection (OCP), and thermal shutdown (TSD).
The ADP2323 operates over the −40°C to +125°C junction
temperature range and is available in a 32-lead LFCSP_WQ
package.
100
95
90
85
80
75
70
65
60 VOUT = 5V
VOUT = 3.3V
55
50
0
0.5 1.0 1.5 2.0 2.5 3.0
OUTPUT CURRENT (A)
Figure 2. Efficiency vs. Output Current at VIN = 12 V, fSW = 600 kHz
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com
1 page  
Data Sheet
Parameters
TRACKING INPUT (TRKx PINS)
TRKx Input Voltage Range
TRKx-to-FBx Offset Voltage
TRKx Input Bias Current
POWER GOOD (PGOODx PINS)
Power Good Rising Threshold
Power Good Hysteresis
Power Good Deglitch Time
PGOODx Leakage Current
PGOODx Output Low Voltage
ENABLE (ENx PINS)
ENx Rising Threshold
ENx Falling Threshold
ENx Source Current
MODE (MODE PIN)
Input High Voltage
Input Low Voltage
THERMAL
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Symbol
Test Conditions/Comments
TRKx = 0 mV to 500 mV
From FBx to PGOODx
VPGOOD = 5 V
IPGOOD = 1 mA
EN voltage below falling threshold
EN voltage above rising threshold
1 Tested in a feedback loop that adjusts VFB to achieve a specified voltage on the COMPx pin.
2 Pin-to-pin measurements.
3 Guaranteed by design.
Min
0
−10
87
1.02
1.3
ADP2323
Typ Max Units
600 mV
+10 mV
100 nA
90 93 %
5%
16 Clock cycle
0.1 1 µA
50 100 mV
1.2 1.28 V
1.1 V
5 µA
1 µA
V
0.4 V
150 °C
15 °C
Rev. A | Page 5 of 32
Free Datasheet http://www.Datasheet4U.com
5 Page 
Data Sheet
660
640
620
600
580
ROSC = 100kΩ
560
540
–40
–20 0 20 40 60 80 100
TEMPERATURE (°C)
Figure 17. Frequency vs. Temperature
120
130
120
110
100
90
80
70
60
50
–40
–20 0 20 40 60 80 100
TEMPERATURE (°C)
Figure 18. MOSFET RDSON vs. Temperature
120
ADP2323
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
4 6 8 10 12 14 16 18 20
VIN (V)
Figure 20. INTVCC Voltage vs. VIN
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
–40 –20 0 20 40 60 80 100
TEMPERATURE (°C)
Figure 21. SSx Pin Source Current vs. Temperature
120
SW
1
DL
2
CH1 5.00V CH2 2.00V
M20.0ns
T 31.20%
A CH1 1.10V
Figure 19. Low-Side Driver Rising Edge Waveform, CDL = 2.2 nF
SW
1
DL
2
CH1 5.00V CH2 2.00V
M20.0ns
T 60.20%
A CH1 1.10V
Figure 22. Low-Side Driver Falling Edge Waveform, CDL = 2.2 nF
Rev. A | Page 11 of 32
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP2323.PDF ] | |
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