PDF HC374 Data sheet ( Hoja de datos )

Número de pieza	HC374
Descripción	Tri-State Octal D-Type Flip-Flops
Fabricantes	RCL Semiconductors
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No Preview Available ! Preliminary Specification RCL Semiconductors Ltd. Tri–State Octal D-Type Flip-Flops (Edge Triggered) HC374 GENERAL DESCRIPTION HC374 is fabricated in the high-speed silicon gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits. It also offers speeds comparable to low power Schottky devices (LS-TTL). These 8-bit flip-flops with 3-state outputs are specifically designed for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bi-directional bus drivers, and working registers. HC374 has octal positive edge triggered D-type flip-flops. On the positive transition of the clock (CK) input, data at the inputs D, meeting the setup and hold time requirement, are transferred to the Q outputs. FEATURES • Wide operating supply voltage range: 2-6V • Output Drive at VDD = 5V : ±6mA • Typical propagation delay: 14ns • Low input current: < 1µA • Low quiescent supply current: 80µA maximum • Octal D-type flip-flops in a single package • Full Parallel access for Loading An output-enable input (OE) places the eight outputs in either a normal logic state (H or L logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. OE should be tied to VDD through a pull-up resistor to ensure the high-impedance state during power up or power down,; the minimum value of the resistor is determined by the current-sinking capability of the driver. LOGIC DIAGRAM D1 3 D1 D2 4 D2 D3 7 D3 D4 8 D4 D5 13 D5 D6 14 D6 D7 17 D7 D8 18 D8 CK 11 C1 C2 C3 C4 C5 C6 C7 C8 1 OE 2 56 9 12 15 16 19 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 3 Dai Fu Street, Tai Po Industrial Estate, Tai Po, N.T. , Hong Kong. Tel : (852)-26659229 Fax : (852)-26652201 1 070209 Free Datasheet http://www.Datasheet4U.com 1 page RCL Semiconductors Ltd. AC TEST CIRCUIT AND AC SWITCHING WAVEFORM HC374 VDD PARAMETER ten tPZH RL 1kΩ CL 50pF or S1 Open tPZL 150pF Closed tdis tPHZ 1kΩ 50pF Open tPLZ tpd or tt Closed --- 50pF or 150pF Open S2 Closed Open Closed Open Open High- Level Pulse Low-Level Pulse 50% tw 50% VVDcDc 50% 0V VVDccD 50% 0 V Voltage Waveforms Pulse Durations Reference Input 50% V tsu th Data Input 50% 10% 90% tr 90% 50 10% tf Voltage Waveforms Setup and Hold and Input rise and Fall times VVDCDC 0V VVDCDC 0V Input 50% tPLH 50% tPHL VVDcDc 0V In-Phase Output 50% 90% 10% tPHL tr 90% Out-of-Phase Output 50% 10% tf 90% VOH 50% 10% VOL tf tPLH 50% 90% VOH 10% VOL tr Voltage Waveforms Propagation Delay and Output Transition Times RCL reserves the right to make changes to this specification at any time without notice 5 Free Datasheet http://www.Datasheet4U.com 5 Page

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