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PDF ICL8068A Data sheet ( Hoja de datos )
| Número de pieza | ICL8068A | |
| Descripción | A/D Converter | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICL8068A (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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itle
L80
AA/
L71
3,
L80
A/IC
1C0
bjec
ecis
Precision 41/2 Digit, A/D Converter
The ICL8052A or ICL8068A/lCL71C03 chip pairs with their
multiplexed BCD output and digit drivers are ideally suited
for the visual display DVM/DPM market. The outstanding
41/2 digit accuracy, 200.00mV to 2.0000V full scale
capability, auto-zero and auto-polarity combine with true
ratiometric operation, almost ideal differential linearity and
time-proven dual slope conversion. Use of these chip pairs
eliminates clock feedthrough problems, and avoids the
critical board layout usually required to minimize charge
injection.
When only 2000 counts of resolution are required, the 71C03
can be wired for 31/2 digits and give up to 30 readings/sec.,
making it ideally suited for a wide variety of applications.
/2
git,
D
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eyw
s
tersi
The ICL71C03 is an improved CMOS plug-in replacement for
the lCL7103 and should be used in all new designs.
Part Number Information
PART NUMBER
lCL8052ACPD
ICL8068ACDD
lCL8068ACJD
TEMP.
RANGE (oC)
PACKAGE
0 to 70 14 Ld PDIP
0 to 70 14 Ld CERDIP
0 to 70 14 Ld CERDIP
lCL71C03ACPl
0 to 70 28 Ld PDIP
PKG.
NO.
E14.3
F14.3
F14.3
E28.6
rpor Pinouts
on,
alog
ICL8052A/ICL8068A
(CERDIP, PDIP)
TOP VIEW
gital
nver
,
D,
crop
esso
erfa
ta
quis
V- 1
COMP OUT 2
14 INT OUT
-1.2V
13 +BUFF IN
REF CAP 3
12 +INT IN
REF BYPASS 4
GND 5 VREF
11 -INT IN
10 -BUFF IN
REF OUT 6
REF SUPPLY 7
9 BUFF OUT
ICL8052A/
ICL8068A
8
V+
ICL8052A/ICL71C03,
ICL8068A/ICL71C03
May 2001
File Number 3081.2
Features
• Typically Less Than 2µVP-P Noise (200.00mV Full Scale,
lCL8068A
• Accuracy Guaranteed to ±1 Count Over Entire ±20,000
Counts (2.0000V Full Scale)
• Guaranteed Zero Reading for 0V Input
• True Polarity at Zero Count for Precise Null Detection
• Single Reference Voltage Required
• Over-Range and Under-Range Signals Available for Auto-
Ranging Capability
• All Outputs TTL Compatible
• Medium Quality Reference, 40ppm (Typ) on Board
• Blinking Display Gives Visual Indication of Over Range
• Six Auxiliary Inputs/Outputs are Available for Interfacing to
UARTs, Microprocessors or Other Complex Circuitry
• 5pA Input Current (Typ) (8052A)
ICL71C03 (PDIP)
TOP VIEW
V+ 1
41/2 / 31/2 2
POL 3
RUN/HOLD 4
COMP IN 5
V- 6
REFERENCE 7
REF. CAP. 1 8
REF. CAP. 2 9
ANALOG IN 10
ANALOG GND 11
CLOCK IN 12
UNDER-RANGE 13
OVER-RANGE 14
28 BUSY
27 D1 (LSD)
26 D2
25 D3
24 D4
23 B8 (MSB)
22 B4
21 B2
20 B1 (LSB)
19 D5 (MSD)
18 STROBE
17 A-Z IN
16 A-Z OUT
15 DIGITAL GND
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001
Free Datasheet http://www.Datasheet4U.com
1 page  
ICL8052A/ICL71C03, ICL8068A/ICL71C03
ICL8052A Electrical Specifications VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
Temperature Coefficient
SYMBOL
TC
TEST
CONDITIONS
MIN TYP MAX UNITS
- 40 - ppm/oC
Supply Voltage (V++ -V-)
Supply Current Total
VSUPPLY
ISUPPLY
±10 - ±16 V
- 6 14 mA
NOTES:
8. The input bias currents are junction leakage currents which approximately double for every 10oC increase in the junction temperature, TJ. Due
to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation the junction
temperature rises above the ambient temperature as a result of internal power dissipation, PD. TJ = TA + RθJAPD, where RθJA is the thermal
resistance from junction to ambient. A heat sink can be used to reduce temperature rise.
9. This is the only component that causes error in dual-slope converter.
System Electrical Specifications: ICL8068A/ICL71C03
V++ = +15V, V+ = +5V, V- = -15V, TA = 25oC, fCLK Set for 3 Readings/Sec.
PARAMETER
TEST
CONDITIONS
ICL8068A/ICL71C03
(NOTE 9)
MIN
TYP
MAX
Zero Input Reading
VIN = 0V,
Full Scale = 200mV
-000.0 ±000.0 +000.0
Ratiometric Error (Note 11)
VIN = VREF
Full Scale = 2V
0.999 1.000 1.001
Linearity Over ± Full Scale (Error of
Reading from Best Straight Line)
-2V ≤ VIN ≤ +2V
- 0.2 1
Differential Linearity (Difference between -2V ≤ VIN ≤ +2V
Worst Case Step of Adjacent Counts and
Ideal Step)
- 0.01 -
Rollover Error (Difference in Reading for -VIN ≅ +VIN ≈ 2V
Equal Positive & Negative Voltage Near
Full Scale)
- 0.2 1
Noise (P-P Value Not Exceeded 95% of VIN = 0V,
-3-
Time)
Full Scale = 200mV
Leakage Current at Input
Zero Reading Drift (Note 12)
Scale Factor Temperature Coefficient
(Note 12)
VIN = 0V
0VoINC=≤
0V,
TA ≤
50oC
VIN = 2V,
0oC
Ext.
≤ TA
Ref.
≤ 50oC
0ppm/oC
- 200 300
- 15
- 3 15
ICL8068A/ICL71C03
(NOTE 10)
MIN
TYP
MAX
-000.0 ±000.0 000.0
0.9999 1.0000 1.0001
- 0.5 1
- 0.01 -
- 0.5 1
-2-
- 100 200
- 0.5 2
- 25
UNITS
Digital
Reading
Digital
Reading
Counts
Counts
Counts
µV
pA
µV/oC
ppm/oC
System Electrical Specifications: ICL8052A/ICL71C03
V++ = +15V, V+ = +5V, V- = -15V, TA = 25oC, fCLK Set for 3 Reading/Sec.
PARAMETER
TEST
CONDITIONS
ICL8052A/ICL71C03
(NOTE 9)
MIN
TYP
MAX
Zero Input Reading
VIN = 0V,
Full Scale = 2V
-0.000 ±0.000 +0.000
Ratiometric Error (Note 11)
VIN = VREF
Full Scale = 2V
0.999 1.000 1.001
Linearity Over ± Full Scale (Error of
Reading from Best Straight Line)
-2V ≤ VIN ≤ +2V
- 0.2 1
ICL8052A/A/ICL71C03
(NOTE 10)
MIN
TYP
MAX
-0.000 ±0.000 0.000
0.9999 1.0000 1.0001
- 0.5 1
UNITS
Digital
Reading
Digital
Reading
Counts
5
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5 Page 
ICL8052A/ICL71C03, ICL8068A/ICL71C03
10-50K
+15V -15V 100kΩ
-BUF IN BUF OUT -INT IN INT OUT
10kΩ
REF
OUT
300pF
1kΩ
8 7 1 10
9
6 BUFFER
INT.
3 REF.
-
A1
+
ICL8068A
5 +BUF IN 13
+INT IN
11 14
INTEG.
COMP.
-
A2 -
+ A3
+2
-1.2V
12
COMP
OUT
-15V
TO ICL7104
FIGURE 6. ADDING BUFFER GAIN TO ICL8068A
Reference Voltage
The analog input required to generate a full scale output is:
VIN = 2VREF.
The stability of the reference voltage is a major factor in the
overall absolute accuracy of the converter. For this reason, it
is recommended that an external high quality reference be
used where ambient temperature is not controlled or where
high-accuracy absolute measurements are being made.
Buffer Gain
At the end of the auto-zero interval, the instantaneous noise
voltage on the auto-zero capacitor is stored and subtracted
from the input voltage while adding to the reference voltage
during the next cycle. The result of this is that the noise
voltage is effectively somewhat greater than the input noise
voltage of the buffer itself during integration. By introducing
some voltage gain into the buffer, the effect of the auto-zero
noise (referred to the input) can be reduced to the level of
the inherent buffer noise. This generally occurs with a buffer
gain of between 3 and 10. Further increase in buffer gain
merely increases the total offset to be handled by the auto-
zero loop, and reduces the available buffer and integrator
swings, without improving the noise performance of the
system. The circuit recommended for doing this with the
ICL8068A/ICL71C03 is shown in Figure 6.
ICL8052A vs ICL8068A
The ICL8052A offers significantly lower input leakage
currents than the ICL8068A, and may be found preferable in
systems with high input impedances. However, the
ICL8068A has substantially lower noise voltage, and is the
device of choice for systems where noise is a limiting factor,
particularly in low signal level conditions.
Max Clock Frequency
The maximum conversion rate of most dual-slope A/D
converters is limited by frequency response of the
comparator. The comparator in this circuit is no exception,
even though it is entirely NPN with an open-loop, gain-
bandwidth product of 300MHz. The comparator output
follows the integrator ramp with a 3µs delay, and at a clock
frequency of 160kHz (6µs period) half of the first reference
integrate clock period is lost in delay. This means that the
meter reading will change from 0 to 1 with 50µV input, 1 to 2
with 150µV, 2 to 3 at 250µV, etc. This transition at midpoint is
considered desirable by most users. However, if the clock
frequency is increased appreciably above 160kHz, the
instrument will flash “1” on noise peaks even when the input
is shorted.
For many dedicated applications where the input signal is
always on one polarity, the dealy of the comparator need not
be limitation. Since the non-linearity and noise do not
increase substantially with frequency, clock rates of up to
approximately 1MHz may be used. For a fixed clock
frequency, the extra count or counts caused by comparator
delay will be a constant and can be subtracted out digitally.
The minimum clock frequency is established by leakage on
the auto-zero and reference caps. With most devices,
measurement cycles as long as 10 seconds give no
measurable leakage error.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz,
40kHz, 331/3kHz, etc, should be selected. For 50Hz
rejection, oscillator frequencies of 250kHz, 1662/3kHz,
125kHz, 100kHz, etc. would be suitable. Note that 100kHz
(2.5 readings/second) will reject both 50Hz and 60Hz.
The clock used should be free from significant phase or
frequency jitter. A simple two-gate oscillator and one based
on CMOS 7555 timer are shown in the Applications section.
The multiplexed output means that if the display takes
significant current from the logic supply, the clock should
have good PSRR.
11
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11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ICL8068A.PDF ] | |
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