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PDF TIP119 Data sheet ( Hoja de datos )

Número de pieza TIP119
Descripción Six Channel 16 bit Quadrature Decoder Counter
Fabricantes TEWS TECHNOLOGIES 
Logotipo TEWS TECHNOLOGIES Logotipo



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No Preview Available ! TIP119 Hoja de datos, Descripción, Manual

The Embedded I/O Company
TIP119
Six Channel 16 bit Quadrature Decoder Counter
Version 1.0
User Manual
Issue 1.1
September 2006
D75119800
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
Phone: +49-(0)4101-4058-0
25469 Halstenbek, Germany Fax: +49-(0)4101-4058-19
www.tews.com
TEWS TECHNOLOGIES LLC
9190 Double Diamond Parkway,
Suite 127, Reno, NV 89521, USA
www.tews.com
Phone: +1 (775) 850 5830
Fax: +1 (775) 201 0347
Free Datasheet http://www.0PDF.com

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TIP119 pdf
Table of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6
FIGURE 2-1 : TECHNICAL SPECIFICATION...................................................................................................7
FIGURE 3-1 : ID PROM CONTENTS ...............................................................................................................8
FIGURE 4-1 : REGISTER SET .........................................................................................................................9
FIGURE 4-2 : COUNTER CHANNEL................................................................................................................9
FIGURE 4-3 : OVERFLOW REGISTER..........................................................................................................10
FIGURE 4-4 : INDEX REGISTER ...................................................................................................................10
FIGURE 4-5 : UP/DOWN REGISTER.............................................................................................................10
FIGURE 4-6 : INTERRUPT VECTOR REGISTER..........................................................................................11
FIGURE 4-7 : INTERRUPT OVERFLOW MASK REGISTER.........................................................................11
FIGURE 4-8 : INTERRUPT INDEX MASK REGISTER ..................................................................................11
FIGURE 6-1 : PIN ASSIGNMENT I/O CONNECTOR.....................................................................................13
FIGURE 6-2 : IP CONNECTOR ORIENTATION ............................................................................................14
TIP119 User Manual Issue 1.1
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TIP119 arduino
4.7 Interrupt Vector Register
Bit
15:8
7:1
0
Symbol Description
-
IVEC
A1
Reserved. Undefined for read access.
Interrupt Vector
Interrupt acknowledge response
This bit reflects the A1 address line during an interrupt
acknowledge cycle
0 – INTRQ0 interrupt acknowledge cycle
1 – INTRQ1 interrupt acknowledge cylce
Figure 4-6 : Interrupt Vector Register
Access Reset
--
W 0xFE
-0
4.8 Interrupt Overflow Mask Register
Bit
15:6
5
4
3
2
1
0
Symbol Description
-
CH6
CH5
CH4
CH3
CH2
CH1
Reserved. Undefined for read access.
Overflow interrupt mask
0 – unmask overflow interrupt.
1 – mask interrupt.
Access Reset
--
W1
W1
W1
W1
W1
W1
Figure 4-7 : Interrupt Overflow Mask Register
Each of the channels interrupts may be masked by setting the interrupt mask register; the overflow
register will have the channel's bit latched asserted but will not cause an interrupt to the host.
4.9 Interrupt Index Mask Register
Bit
15:6
5
4
3
2
1
0
Symbol Description
-
CH6
CH5
CH4
CH3
CH2
CH1
Reserved. Undefined for read access.
Index interrupt mask
0 – unmask Index interrupt.
1 – mask interrupt.
Access Reset
--
W1
W1
W1
W1
W1
W1
Figure 4-8 : Interrupt Index Mask Register
Each of the channels interrupts may be masked by setting the interrupt mask register; the index
register will have the channel's bit latched asserted but will not cause an interrupt to the host.
TIP119 User Manual Issue 1.1
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