DataSheetWiki


NT5CB512M8CN fiches techniques PDF

Nanya - Industrial and Automotive DDR3(L) 4Gb SDRAM

Numéro de référence NT5CB512M8CN
Description Industrial and Automotive DDR3(L) 4Gb SDRAM
Fabricant Nanya 
Logo Nanya 





1 Page

No Preview Available !





NT5CB512M8CN fiche technique
DDR3(L) 4Gb SDRAM
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Nanya Technology Corp.
NT5CB(C)512M8CN / NT5CB(C)256M16CP
Commercial, Industrial and Automotive DDR3(L) 4Gb SDRAM
Features
JEDEC DDR3 Compliant
- 8n Prefetch Architecture
- Differential Clock(CK/) and Data Strobe(DQS/)
- Double-data rate on DQs, DQS and DM
Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
Power Saving Mode
- Partial Array Self Refresh (PASR)1
- Power Down Mode
Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
Signal Synchronization
- Write Leveling via MR settings
- Read Leveling via MPR
Interface and Power Supply
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)
- SSTL_1354 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)
Speed Grade (CL-TRCD-TRP) 2,3
- 2133 Mbps / 14-14-14
- 1866 Mbps / 13-13-13
- 1600 Mbps / 11-11-11
Options
Temperature Range (Tc) 5
- Commercial Grade = 0~95
- Industrial Grade = -40~95
- Automotive Grade 2 = -40~105
- Automotive Grade 3 = -40~95
Programmable Functions
CAS Latency (5/6/7/8/9/10/11/12/13/14)
CAS Write Latency (5/6/7/8/9/10)
Additive Latency (0/CL-1/CL-2)
Write Recovery Time (5/6/7/8/10/12/14/16)
Burst Type (Sequential/Interleaved)
Burst Length (BL8/BC4/BC4 or 8 on the fly)
Self RefreshTemperature Range(Normal/Extended)
Output Driver Impedance (34/40)
On-Die Termination of Rtt_Nom(20/30/40/60/120)
On-Die Termination of Rtt_WR(60/120)
Precharge Power Down (slow/fast)
Packages / Density Information
Lead-free RoHS compliance and Halogen-free
Density and Addressing
4Gb
(Org. / Package)
Length x Width
(mm)
Ball pitch
(mm)
512Mbx8
78-ball
TFBGA
9.00 x 10.50
0.80
256Mbx16
96-ball
TFBGA
9.00 x 13.00
0.80
Organization
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page Size
tRFC(ns) 6
512Mb x 8
BA0 BA2
A10 / AP
A12 / 
A0 A15
A0 A9
1KB
260ns
256Mb x 16
BA0 BA2
A10 / AP
A12 / 
A0 A14
A0 A9
2KB
260ns
Notes:
1. Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.
2. The timing specification of high speed bin is backward compatible with low speed bin.
3. Please refer to ordering information for the deailts (DDR3, DDR3L, DDR3L RS).
4. SSTL_135 compatible to SSTL_15.
5. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled.
6. Violating tRFC specification will induce malfunction.
1
Version 1.3
08/ 2013
Nanya Technology Cooperation ©
All Rights Reserved.
Free Datasheet http://www.0PDF.com

PagesPages 70
Télécharger [ NT5CB512M8CN ]


Fiche technique recommandé

No Description détaillée Fabricant
NT5CB512M8CN Industrial and Automotive DDR3(L) 4Gb SDRAM Nanya
Nanya

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche