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PDF D64084 Data sheet ( Hoja de datos )
| Número de pieza | D64084 | |
| Descripción | UPD64084 | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD64084
THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
DESCRIPTION
The µPD64084 realizes a high precision Y/C separation by the three-dimension signal processing for NTSC signal.
This product has the on-chip 4-Mbit memory for flame delay, a high precision internal 10-bit A/D converter and D/A
converter, and adapting 10-bit signal processing (only for luminance signal) and high picture quality. The µPD64084 is
completely single-chip system of 3D Y/C separation.
This LSI includes the Wide Clear Vision ID signal (Japanese local format) decoder and ID-1 signal decoder.
FEATURES
• On-chip 4-Mbit frame delay memory.
• 2 operation mode
Motion adaptive 3D Y/C separation
2D Y/C separation + Frame recursive Y/C NR
• Embedded 10-bit A/D converter (1ch), 10-bit D/A converters (2ch), and System clock generator.
• Embedded Y coring, Vertical enhancer, Peaking filter, and Noise detector.
• Embedded ID-1 signal decoder, and WCV-ID signal decoder.
• I2C bus control.
• Dual power supply of 2.5 V and 3.3 V.
For digital : DVDD = 2.5 V
For analog : AVDD = 2.5 V
For DRAM : DVDDRAM = 2.5 V
For I/O : DVDDIO = 3.3 V
ORDERING INFORMATION
Part number
µPD64084GC-8EA-ANote1
µPD64084GC-8EA-YNote2
Package
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Notes 1. Lead-free product
2. High-thermal-resistance product
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16021EJ2V0DS00 (2nd edition)
Date Published March 2003 NS CP (K)
Printed in Japan
The mark shows major revised points.
2002
Free Datasheet http://www.0PDF.com
1 page  
TERMINOLOGY
This manual use the abbreviation listed below:
ADC
: A/D (Analog to Digital) converter
DAC
: D/A (Digital to Analog) converter
LPF : Low-pass filter
BPF : Band-pass filter
Y signal, or Luma : Luminance, or luminance signal
C signal, or Chroma : Color signal, or chrominance signal
fSC : Color subcarrier frequency = 3.579545 MHz
4fSC : 4 times fSC, burst locked clock = 14.318180 MHz
8fSC : 8 times fSC, burst locked clock = 28.636360 MHz
fH : Horizontal sync frequency = 15.734 kHz
910fH
: 910 times fH, line locked clock = 14.318180 MHz
1820fH : 1820 times fH, line locked clock = 28.636360 MHz
fV : Vertical sync frequency = 59.94 Hz
NR : Noise reduction
YNR
: Luminance (Y) noise reduction
CNR
: Chrominance (C) noise reduction
WCV-ID : Wide Clear Vision standard ID signal (Japan only)
ID-1 : ID signal of EIAJ CPR-1204
In the following diagrams, a serial bus register is enclosed in a box:
µ PD64084
Data Sheet S16021EJ2V0DS
5
Free Datasheet http://www.0PDF.com
5 Page 
µ PD64084
2. SYSTEM OVERVIEW
2.1 Operation Modes
The µPD64084 can operate in the following major four signal processing modes. Mode selection is performed
according to NRMD on the serial bus.
Serial bus setting Function Note
Mode name
NRMD = 0
YCS mode
Y/C separation
Table 2-1. Operation Modes
Pin input
System clock
Feature Model diagram
AYI : Composite signal
Burst locked clock
(4fSC, 8fSC)
• For standard signals, motion-adaptive three-
dimensional Y/C separation is performed.
• For nonstandard signals, inter-line Y/C
separation is performed.
Comp.
ADC
4fSC
YCS
(3D/2D)
Y
DAC
C
DAC
NRMD = 1
YCS+ mode
2D Y/C
separation
and YCNR
4-Mbit memory
AYI : Composite signal
Burst locked clock
(4fSC, 8fSC)
• Inter-line Y/C separation and Frame recursive
YNR and CNR is performed.
Comp.
ADC
4fSC
YCS
(2D)
YNR
Y
DAC
C
CNR DAC
4-Mbit memory
Note 3D Y/C separation, Frame-recursive YNR/CNR, each function is independence. So these don't operate at the
same time.
Data Sheet S16021EJ2V0DS
11
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