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PDF LXT350 Data sheet ( Hoja de datos )
| Número de pieza | LXT350 | |
| Descripción | T1/E1 Short Haul Transceiver | |
| Fabricantes | Intel | |
| Logotipo |  |
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LXT350
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Datasheet
The LXT350 is a full-featured, fully-integrated transceiver for T1 and E1 short-haul
applications. The LXT350 is software switchable between T1 and E1 operation, and offers pulse
equalization settings for all short-haul T1 and E1 line interface (LIU) applications.
LXT350 provides both a serial port for microprocessor control (Host mode) as well as stand-
alone operation (Hardware mode). The device incorporates advanced crystal-less digital jitter
attenuation in either the transmit or receive data path starting at 3 Hz. B8ZS/HDB3 encoding/
decoding and unipolar or bipolar data I/O are selectable. Loss of signal monitoring and a variety
of diagnostic loopback modes can also be selected.
Applications
s SONET/SDH tributary interfaces
s Digital cross connects
Product Features
s Public/private switching trunk line
interfaces
s Microwave transmission systems
s Fully integrated transceivers for Short-Haul
T1 or E1 interfaces
s Crystal-less digital jitter attenuation
— Select either transmit or receive path
— No crystal or high speed external clock
required
s Meet or exceed specifications in ANSI
T1.403 and T1.408; ITU I.431, G.703,
G.736, G.775 and G.823; ETSI 300-166
and 300-233; and AT&T Pub 62411
s Supports 75 Ω (E1 coax), 100 Ω (T1
twisted-pair) and 120 Ω (E1 twisted-pair)
applications
s Fully restores the received signal after
transmission through a cable with
attenuation of 18dB, at 1024 kHz
s Five pulse equalization settings for T1
short-haul applications
s Transmit/receive performance monitors
with Driver Fail Monitor Open (DFM) and
Loss of Signal (LOS) outputs
s Selectable unipolar or bipolar data I/O and
B8ZS/HDB3 encoding/decoding
s QRSS generator/detector for testing or
monitoring
s Output short circuit current limit protection
s Local, remote and analog loopback
capability
s Compatible with Intel’s LXT360/361 T1/
E1 long haul/short haul transceiver
(Universal LIU)
s Multiple register serial interface for
microprocessor control
s Available in 28-pin PLCC and 44-pin
PQFP packages
As of January 15, 2001, this document replaces the Level One document
Order Number: 249029-001
LXT350 — Integrated T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation.
January 2001
Free Datasheet http://www.nDatasheet.com
1 page  
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LXT350 Clock and Data Pins by Mode1 ............................................................... 9
LXT350 Control Pins by Mode ..............................................................................9
LXT350 Signal Descriptions ................................................................................10
CLKE Pin Settings1.............................................................................................18
Control and Operational Mode Selection ............................................................19
Diagnostic Mode Availability................................................................................19
Register Addresses .............................................................................................28
Register and Bit Summary ..................................................................................28
Control Register #1 Read/Write, Address (A7-A0) = x010000x ..........................29
Equalizer Control Input Settings.........................................................................29
Control Register #2 Read/Write, Address (A7-A0) = x010001x ..........................29
Control Register #3 Read/Write, Address (A7-A0) = x010010x ..........................30
Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x....................30
Transition Status Register Read Only, Address (A7-A0) = x010100x.................31
Performance Status Register Read Only, Address (A7-A0) = x010101x ............31
Control Register #4 Read/Write, Address (A7-A0) = x010111x ..........................32
E1 Transmit Return Loss Requirements .............................................................33
Transmit Return Loss (2.048 Mbps)....................................................................34
Transmit Return Loss (1.544 Mbps)....................................................................34
Transformer Specifications..................................................................................34
Recommended Transformers..............................................................................35
Absolute Maximum Ratings.................................................................................38
Recommended Operating Conditions .................................................................38
DC Electrical Characteristics...............................................................................39
Analog Characteristics ........................................................................................39
2.048 MHz E1 Pulse Mask Specifications...........................................................41
1.544 Mbps T1, DSX-1 Pulse Mask Corner Point Specifications........................42
T1 Operation Master and Transmit Clock Timing Characteristics
(See Figure 16) ...................................................................................................43
E1 Operation Master and Transmit Clock Timing Characteristics
(See Figure 16) ...................................................................................................43
Receive Timing Characteristics for T1 Operation (See Figure 17)......................44
Receive Timing Characteristics for E1 Operation (See Figure 17) .....................44
Serial I/O Timing Characteristics (See Figure 18 and Figure 19)........................45
Datasheet
5
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5 Page 
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Table 3. LXT350 Signal Descriptions (Continued)
Pin #
PLCC QFP
Symbol
I/O1
Description
97
TRSTE
Tristate.
HARDWARE MODES:
Connect TRSTE High to force all output pins to the high impedance state.
DI
TRSTE, in conjunction with the MODE pin, selects the operating modes listed
in Table 5 on page 19.
HOST MODES:
Connect TRSTE High to force all output pins to the high-impedance state.
Connect this pin Low for normal operation.
11 10
JASEL
HARDWARE MODES:
Jitter Attenuation Select. Selects jitter attenuation location:
Setting JASEL High activates the jitter attenuator in the receive path.
DI Setting JASEL Low activates the jitter attenuator in the transmit path.
Setting JASEL to Midrange2 disables jitter attenuation.
HOST MODES:
Connect Low in Host mode.
12 13
LOS / QPD
Loss of Signal Indicator. LOS goes High upon receipt of 175 consecutive
spaces and returns Low when the received signal reaches a mark density of
12.5% (determined by receipt of 16 marks within a sliding window of 128 bits
with fewer than 100 consecutive zeros). Note that the transceiver outputs
received marks on RPOS and RNEG even when LOS is High.
DO
QRSS Pattern Detect. In QRSS mode, QPD stays High until the transceiver
detects a QRSS pattern. When a QRSS pattern is detected, the pin goes Low.
Any bit errors cause QPD to go High for half a clock cycle. This output can be
used to trigger an external error counter. Note that a LOS condition will cause
QPD to remain High. See Figure 11.
13 15
16 19
TTIP
TRING
Transmit Tip and Ring. Differential driver output pair designed to drive a 50 -
AO
200 Ω load. The transformer and line matching resistors should be selected to
give the desired pulse height and return loss performance. See “Application
Information” on page 33.
14 16
TGND
- Ground return for the transmit driver power supply TVCC.
15 18
TVCC
-
+5 VDC Power Supply for the transmit drivers. TVCC must not vary from VCC
by more than ± 0.3 V.
17 20
GND
- Tie to Ground.
19 24
20 25
RTIP
RRING
Receive Tip and Ring. The Alternate Mark Inversion (AMI) signal received
AI
from the line is applied at these pins. A 1:1 transformer is required. Data and
clock recovered from RTIP/RRING are output on the RPOS/RNEG (or RDATA
in Unipolar mode), and RCLK pins.
21 27
VCC
-
+5 VDC Power Supply for all circuits except the transmit drivers. Transmit
drivers are supplied by TVCC.
22 29
GND
- Ground return for power supply VCC.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
2. Midrange is a voltage level such that 2.3 V ≤ Midrange ≤ 2.7 V. Midrange may also be established by letting the pin float.
Datasheet
11
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