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Número de pieza | HEF4753B | |
Descripción | Universal timer module | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4753B
LSI
Universal timer module
Product specification
File under Integrated Circuits, IC04
January 1995
1 page Philips Semiconductors
Universal timer module
Product specification
HEF4753B
LSI
2. Divider mode (LFC = LOW; Y = HIGH; Z = LOW)
In this mode the output OUT should be connected to input IN. If not, only one counter cycle starts after a transition at
input IN (see Fig.4 and note 1.).
A B C D E F G H W X LFC Y Z
L L H H H H HH L L L H L
Fig.4 Timing diagram for divider mode; t1 = delay until set of 8-bit counter; t2, t3 see Fig.3.
3. Delayed LOW to HIGH edge mode; see note 2. (LFC = HIGH; Y = HIGH; Z = LOW)
A B C D E F G H W X LFC Y Z
H L HHH H H H L L H H L
Fig.5 Timing diagram for delayed LOW to HIGH edge mode; t1 = delay until set of 8-bit counter; t2 = delay to
set 8-bit counter; t3 = predefined delay by programming; t4 = delay until next negative clock edge;
t5 = delay until next positive clock edge.
January 1995
5
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet HEF4753B.PDF ] |
Número de pieza | Descripción | Fabricantes |
HEF4753B | Universal timer module | NXP Semiconductors |
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