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PDF ICS95V847 Data sheet ( Hoja de datos )
| Número de pieza | ICS95V847 | |
| Descripción | 2.5V Wide Range Frequency Clock Driver | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS95V847 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS95V8 47
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
Recommended Application:
• Zero Delay Board Fan Out, SO-DIMM
• Provides complete DDR registered DIMM solution
with ICSSSTV16857, ICSSSTV16859 or
ICSSSTV32852
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 5 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
Switching Characteristics:
• CYCLE - CYCLE jitter: <60ps
• OUTPUT - OUTPUT skew: <60ps
• Period jitter: ±30ps
• DUTY CYCLE: 49.5% - 50.5%
Pin Configuration
GND
CLKC0
CLKT0
GND
VDD
CLK_INT
CLK_INC
AVDD
AGND
CLKC1
CLKT1
VDD
1
2
3
4
5
6
7
8
9
10
11
12
24 CLKT4
23 CLKC4
22 CLKC3
21 CLKT3
20 VDD
19 FB_INT
18 FB_INC
17 FB_OUTC
16 FB_OUTT
15 CLKT2
14 CLKC2
13 GND
24-Pin TSSOP
4.40 mm. Body, 0.65 mm. pitch
Functionality
Block Diagram
INPUTS
OUTPUTS
AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
PLL State
GND
L
H LH L
H Bypassed/off
GND
2.5V
(nom)
2.5V
(nom)
H
L
H
L HL H
H LH L
L HL H
L Bypassed/off
H on
L on
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
0718D—04/08/05
Free Datasheet http://www.nDatasheet.com
1 page  
ICS95V8 47
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Max clock frequency
freqop
2.5V+0.2V @ 25oC
45 233
Application Frequency
Range
freqApp
2.5V+0.2V @ 25oC
95 210
Input clock duty cycle
dtin
40 60
UNITS
MHz
MHz
%
CLK stabilization
TSTAB
15 µs
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
Low-to high level
propagation delay time
tPLH1
CLK_IN to any output
High-to low level propagation
delay time
tPLL1
CLK_IN to any output
Output enable time
Output disable time
tEN PD# to any output
tdis PD# to any output
Period jitter
Half-period jitter
Tjit (per)
t(jit_hper)
100MHz to 200MHz
100MHz to 200MHz
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter1
Phase error
Output to Output Skew
tsl(i)
tsl(o)
Tcyc-Tcyc
t(phase
4
error)
Tskew
100MHz to 200MHz
MIN TYP
5.5
5.5
5
5
-30
-75
1
1
-50 0
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
MAX UNITS
ns
ns
ns
ns
30 ps
30 ps
4 V/ns
2.5 V/ns
60 ps
50 ps
60 ps
0718D—04/08/05
5
Free Datasheet http://www.nDatasheet.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet ICS95V847.PDF ] | |
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