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PDF HI-6121 Data sheet ( Hoja de datos )
| Número de pieza | HI-6121 | |
| Descripción | (HI-6120 / HI-6121) MIL-STD-1553 Remote Terminal ICs | |
| Fabricantes | Holt Integrated Circuits | |
| Logotipo |  |
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November, 2015
HI-6120 Parallel Bus Interface and
HI-6121 Serial Peripheral Interface (SPI)
MIL-STD-1553 Remote Terminal ICs
GENERAL DESCRIPTION
The HI-6120 and HI-6121 provide a complete, integrated,
3.3V MIL-STD-1553 Remote Terminal in a monolithic sili-
con gate CMOS device. Two host interface options are
offered: The HI-6120 uses a 16-bit parallel host bus inter-
face for access to registers and RAM and is offered in a
100-pin plastic quad flat pack (PQFP). The HI-6121 has
a 4-wire SPI (Serial Peripheral Interface) host connection
and comes in a reduced pin count 52-pin PQFP or 9mm
x 9mm 64-pin QFN. Both devices handle all aspects of
the MIL-STD-1553 protocol, including message encod-
ing, decoding, error detection, illegal command detection
and data buffering. Host data management is simplified
by storing message information and data within the on-
chip 32K x 16 static RAM.
A descriptor table in shared RAM provides fully program-
mable memory management. Multiple descriptor tables
can be implemented for fast context switching. Trans-
mit and receive commands can use any of four differ-
ent data buffer modes: indexed (single) buffering, ping-
pong (double) buffering or two circular buffer schemes.
Transmit and receive commands for each subaddress
may use different buffer modes. Mode code commands
employ a simple scheme for storing mode data and mes-
sage information with programmable interrupts.
The device provides internal illegalization capability,
allowing any subset of subaddress, command T/R bit,
broadcast vs non-broadcast and word count (or mode
code) to be illegalized, resulting in a total of 4,096 pos-
sible combinations. The illegalization table resides in in-
ternal RAM. The RT can also operate without illegal com-
mand detection, providing “in form” responses to all valid
commands. Broadcast command recognition is optional.
The HI-6120 and HI-6121 provide programmable inter-
rupts for automatic message handling, message status
and general status. A host interrupt history log maintains
information about the last 16 interrupts.
The HI-6120 and HI-6121 can be configured for automat-
ic self-initialization. A dedicated SPI port reads data from
external serial EEPROM memory to fully configure the
descriptor table, illegalization table and host interrupts.
Internal dual-redundant transceivers provide direct
connection to bus isolation transformers. The device
is offered with industrial temperature range as well as
extended temperature range with optional burn-in. A
“RoHS compliant” lead-free option is also offered.
FEATURES
• Fully integrated 3.3V Remote Terminal meets all
requirements for MIL-STD-1553B Notice 2
• Four data buffer modes for subaddress transmit
and receive commands. Data buffer modes are
independently selectable for transmit and receive
commands on each subaddress
• Simplified mode code command handling
• Integral 16-bit Time-Tag counter has programma-
ble options for clock, interrupts and auto-synchro-
nization
• Message information and time-tag words are
stored with message data words for all transacted
messages
• In compliance with MIL-STD-1553B Notice 2, re-
ceived data from broadcast messages may be
optionally separated from non-broadcast received
data
• Optional interrupt log buffer stores the most recent
16 interrupts to minimize host service duties
• Optional illegal command detection uses internal
table
• Optional automatic self-initialization at reset
• ±8kV ESD Protection (HBM, all pins)
• MIL-STD-1760 compliant
PIN CONFIGURATION (TOP)
COMP - 1
CE - 2
MODE - 3
SI - 4
SCK - 5
SO - 6
MCLK - 7
RTA0 - 8
RTA1 - 9
RTA2 - 10
MR - 11
RTA3 - 12
RTA4 - 13
HI-6121PQx
HI-6121 in
PQFP-52 Package
39 - TEST
38 - LOCK
37 - MTSTOFF
36 - BUSA
35 - VCCP
34 - BUSA
33 - BUSB
32 - VCCP
31 - BUSB
30 - TEST0
29 - TEST3
28 - TEST2
27 - TEST1
DS6120 Rev. I
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
11/15
1 page  
HI-6120, HI-6121
11.4.2. Broadcast Message Handling in Index Mode.............................................................. 84
11.5. Circular Buffer Mode 1................................................................................................. 88
11.6. Circular Buffer Mode 2................................................................................................. 92
12. MODE COMMAND PROCESSING................................................................... 97
12.1. General Considerations............................................................................................... 97
12.2. Mode Command Interrupts.......................................................................................... 97
12.3. Mode Command Data Words...................................................................................... 97
12.4. Standard Mode Command Processing..................................................................... 100
12.5. Simplified Mode Command Processing.................................................................... 100
13. INTERRUPT MANAGEMENT......................................................................... 101
13.1. Host Message Detection Options.............................................................................. 101
13.2. Host Interrupt Generation.......................................................................................... 101
13.2.1. Interrupt Log Address Register.................................................................................. 102
13.2.2. Interrupt Address Word (IAW).................................................................................... 102
13.2.3. Interrupt Identification Word (IIW)............................................................................. 102
14. RESET AND INITIALIZATION......................................................................... 103
14.1. Master Reset using the MR pin and Optional Auto-Initialization............................... 103
14.2. Software Reset.......................................................................................................... 107
14.3. Reset Remote Terminal Mode Code......................................................................... 107
14.4. Serial EEPROM Programming Utility ....................................................................... 107
14.5. MIL-STD-1760: Busy Status Assertion After Power-Up............................................ 109
15. HOST INTERFACE......................................................................................... 110
15.1. HI-6120 Host Bus Interface....................................................................................... 110
15.1.1. Bus Wait States and Data Prefetch............................................................................ 110
15.2. HI-6121 Serial Peripheral Interface............................................................................111
15.2.1. Serial Peripheral Interface (SPI) Basics .....................................................................111
15.2.2. HI-6121 SPI Commands............................................................................................ 112
15.2.3. Fast-Access Commands for Registers 0-15 ............................................................. 112
15.2.4. Indirect Addressing of RAM and Registers ............................................................... 112
15.2.5. Data Prefetch for SPI Read Cycles............................................................................ 114
15.2.6. Special Purpose Commands..................................................................................... 114
15.2.7. Descriptor Table Prefetch Exceptions........................................................................ 116
16. APPENDIX: RT MESSAGES RESPONSES, OPTIONS & EXCEPTIONS .... 120
HOLT INTEGRATED CIRCUITS
5
5 Page 
HI-6120, HI-6121
2. PIN DESCRIPTIONS
Table 1. Pin Descriptions (Both HI-6120 and HI-6121)
Pin
INTHW
INTMES
MR
MTSTOFF
EECOPY
AUTOEN
EE1K
RTA4:0
RTAP
LOCK
TXINHA
TXINHB
Function Description
OUTPUT
Hardware Interrupt output, active low.This signal is programmed as a brief
low-going pulse output, or as a level output by the INTSEL bit in Configuration
Register 1.
OUTPUT
Message Interrupt output, active low. This signal is programmed as a brief low-
going pulse output, or as a level output by the INTSEL bit in Configuration
Register 1.
INPUT
Master Reset, active low. Internal 50kΩ pull-up resistor. The host can also assert
software reset by setting the SRST bit in Configuration Register 1.
INPUT
Memory test disable, active high. Internal 50kΩ pull-down resistor. When this pin
is low, the device performs a memory test on the entire RAM after rising edge on
the MR reset pin. When this pin is high, the RAM test is skipped, resulting in a
faster reset process. For further information, refer to Section 14 on page 103.
INPUT
EEPROM Copy, active high. Internal 50kΩ pull-down resistor. This input is used to
start the process that copies registers and configuration tables to serial EEPROM.
Refer to Section 14 on page 103.
INPUT
Auto-Initialize Enable, active high. Internal 50kΩ pull-down resistor. If this pin is
high at rising edge on MR reset input, automatic initialization proceeds, copying
configuration data to registers and RAM from an external serial EEPROM via the
dedicated auto-initialization SPl port. Refer to Section 14 on page 103.
INPUT
When the AUTOEN pin is high, the EE1K input sets the range of the auto-
initialization process. When EE1K is low, registers and RAM occupying the 32K
address range from 0x0 to 0x7FFF are initialized. For applications needing faster
initialization, when EE1K is high, only registers and RAM occupying the 1K
address range from 0x0 to 0x03FF are initialized. This pin has an internal 50kΩ
pull-down resistor. If the AUTOEN pin is low, this pin is not used. Refer to Section
14 on page 103.
INPUTS
Remote terminal address bits 4 - 0, and parity bit. Internal 50kΩ pull-up resistors.
The RTAP pin should provide odd parity for the address present on pins RTA4:0.
Terminal address and parity pin levels are latched into the Operational Status
register when rising edge occurs on the MR pin. The Operational Status Register
value (not these pins) reflects the active terminal address. The register value can
be overwritten by the host under some circumstances. See section 5.3 on page
28.
INPUT
Internal 50kΩ pull-down resistor. Pin state is latched into the Operational Status
register LOCK bit when rising edge occurs on the MR pin. If Operational Status
register LOCK bit is high, terminal address in the register cannot be overwritten by
a host register write. If Operational Status register LOCK bit is low, the host can
overwrite the five terminal address bits and address parity bit in the Operational
Status register.
INPUTS
Transmit Inhibits for Bus A and Bus B, active high. Internal 50kΩ pull-down
resistors. These inputs are logically ORed with the corresponding TXINHA and
TXINHB bits in Configuration Register 1. If the input pin or register bit is high, bus
transmit is disabled.
HOLT INTEGRATED CIRCUITS
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HI-6121.PDF ] | |
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