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PDF M306NAFGTFP Data sheet ( Hoja de datos )
| Número de pieza | M306NAFGTFP | |
| Descripción | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER | |
| Fabricantes | Renesas | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Free Datasheet http://www.datasheetlist.com/
1 page  
Description
Block Diagram
Figure 1.1.3 is a block diagram of the M16C/6N group.
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block diagram of the M16C/6N group
88
8
88
88
I/O ports
Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6
Internal peripheral functions
Timer
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
Watchdog timer
(15 bits)
DMAC
(2 channels)
D-A converter
(8 bits x 2 channels)
A-D converter
(10 bits X (8X3+2) channels)
System clock generator
XIN - XOUT
XCIN - XCOUT
Ring oscillator
UART/clock synchronous SI/O
(8 bits X 3 channels)
Clock synchronous SI/O
(8 bits X 1 channel)
CRC arithmetic circuit (CCITT)
(Polynomial : X16+X12+X5+1)
CAN module
(1 or 2 channels)
(Note 2)
M16C/60 series16-bit CPU core
Registers
RRRR10HH01HH RRR10RLL01LL
RRR232
ARA030
FABA1FB1
SB
Program counter
PC
Vector table
INTB
Stack pointer
ISP
USP
Flag register
FLG
Memory
ROM
(Note 1)
RAM
(Note 1)
Multiplier
Note 1: Memory sizes depend on MCU type.
Note 2: Number of channels depends on sub-group.
Figure 1.1.3. Block diagram of M16C/6N group
4
Free Datasheet http://www.datasheetlist.com/
5 Page 
Memory
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Operation of Functional Blocks
The M16C/6N group accommodates several units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as CAN module, timers, serial I/O, D-A converter, DMAC, CRC
calculation circuit, A-D converter, and I/O ports.
Each unit is explained in the following.
Memory
Figure 1.3.1 shows the memory map of the M16C/6N group. The address space extends the 1M bytes from
address 0000016 to FFFFF16. The ROM area is mapped top-aligned up to FFFFF16. The start address
depends on the memory capacity of the device; e.g. 128Kbytes ROM are mapped E000016 up to FFFFF16.
______
The vector table for fixed interrupts such as the reset and NMI are mapped to FFFDC16 to FFFFF16. The
starting addresses of the interrupt routines are stored here. The address of the vector table for timer inter-
rupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details.
The RAM area is mapped bottom-aligned starting from 0040016. The end address depends on the RAM
capacity of the device; e.g. 5Kbytes RAM are mapped to 0040016 to 017FF16. In addition to storing data,
the RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, CAN modules and timers, etc. Figure 1.6.1 to 1.6.3
show the locations of peripheral unit control registers. Any part of the SFR area that is not occupied is
reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be implemented as 2-byte instructions, reducing the number of program steps.
Depending on processor mode setting, a part of the space is reserved and cannot be used. For example, in
the M306NAMCT-XXXFP, the following space cannot be used.
• The space between 0180016 and 03FFF16 (All modes)
• The space between 0400016 and CFFFF16 (Single-chip mode)
• The space between D000016 and DFFFF16 (Single-chip mode and memory expansion mode)
For details on how to enable usage of specific memory areas, see the section "Processor Mode".
Note 1: Cannot be used in any mode.
Note 2: Cannot be used in single-chip mode.
Note 3: Cannot be used in single-chip mode or memory
expansion mode.
Type No.
M306NBMCT/FCT
M306NAMCT
M306NAMGT
M306NAFGT
Address XXXXX16
017FF16
017FF16
02BFF16
02BFF16
Address YYYYY16
E000016
E000016
C000016
C000016
PM13 (Note)
Address MMMMM16
Address NNNNN16
0 0400016 D000016
1 0600016 C000016
Note: PM13 (Internal reserved area expansion bit)
0000016
SFR area
0040016
XXXXX16
MMMMM16
Internal RAM area
Internal reserved
area (Note 1)
External area
(Note 2)
NNNNN16
YYYYY16
Internal reserved
area (Note 3)
Internal ROM area
FFFFF16
Figure 1.3.1. Memory map
10
FFE0016
Special page
vector table
FFFDC16
FFFFF16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Oscillation stop detection/Watchdog timer
DBC
NMI
Reset
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