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PDF K9WBG08U1M Data sheet ( Hoja de datos )
| Número de pieza | K9WBG08U1M | |
| Descripción | FLASH MEMORY | |
| Fabricantes | Samsung | |
| Logotipo |  |
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K9WBG08U1M
K9KAG08U0M K9NCG08U5M
FLASH MEMORY
K9XXG08XXM
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
Free Datasheet http://www.datasheetlist.com/
1 page  
K9WBG08U1M
K9KAG08U0M K9NCG08U5M
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9WBG08U1M-PCX0/PIX0
N.C
N.C
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
48 N.C
47 N.C
46 N.C
45 N.C
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 N.C
39 N.C
38 N.C
37 Vcc
36 Vss
35 N.C
34 N.C
33 N.C
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 N.C
27 N.C
26 N.C
25 K9WBG08U1MN.C
PACKAGE DIMENSIONS
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1 #48
#24
0~8°
0.45~0.75
0.018~0.030
18.40±0.10
0.724±0.004
5
#25
1.00±0.05
0.039±0.002
01..02407MAX
0.05
0.002
MIN
(
0.50
0.020
)
Free Datasheet http://www.datasheetlist.com/
5 Page 
K9WBG08U1M
K9KAG08U0M K9NCG08U5M
FLASH MEMORY
Product Introduction
The K9KAG08U0M is a 16,896Mbit(17,716,740,096 bit) memory organized as 524,288 rows(pages) by 4,224x8 columns. Spare
128x8 columns are located from column address of 4,096~4,223. A 4,224-byte data register is connected to memory cell arrays
accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory
array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A
block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 2,162,688 NAND cells reside in a block.
The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 8,192 separately erasable 256K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9KAG08U0M.
The K9KAG08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 2,112M byte physical space
requires 32 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-
ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the
command register. Table 1 defines the specific commands of the K9KAG08U0M.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
11
Free Datasheet http://www.datasheetlist.com/
11 Page | ||
| Páginas | Total 69 Páginas | |
| PDF Descargar | [ Datasheet K9WBG08U1M.PDF ] | |
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