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PDF HEF4557B Data sheet ( Hoja de datos )
| Número de pieza | HEF4557B | |
| Descripción | 1-to-64 bit variable length shift register | |
| Fabricantes | NXP Semiconductors | |
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HEF4557B
1-to-64 bit variable length shift register
Rev. 6 — 18 November 2011
Product data sheet
1. General description
The HEF4557B is a static clocked serial shift register whose length may be programmed
to be any number of bits between 1 and 64. The number of bits selected is equal to the
sum of the subscripts of the enabled length control inputs (L1, L2, L4, L8, L16, and L32)
plus one. Serial data may be selected from the DA or DB data inputs with the A/B select
input. This feature is useful for recirculation purposes. Information on DA or DB is shifted
into the first register position and all the data in the register is shifted one position to the
right on the LOW to HIGH transition of CP0 while CP1 is LOW or on the HIGH to LOW
transition of CP1 while CP0 is HIGH. A HIGH on master reset (MR) resets the register and
forces Q to LOW and Q to HIGH, independent of the other inputs.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C
Type number
Package
Name
Description
HEF4557BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
HEF4557BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1
1 page  
NXP Semiconductors
HEF4557B
1-to-64 bit variable length shift register
7. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDD
IIK
VI
IOK
II/O
IDD
Tstg
Tamb
Ptot
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
DIP16 package
SO16 package
P power dissipation
per output
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions
Min
0.5
-
0.5
-
-
-
65
40
[1] -
[2] -
-
Max
+18
10
VDD + 0.5
10
10
50
+150
+85
750
500
100
Unit
V
mA
V
mA
mA
mA
C
C
mW
mW
mW
Table 6.
Symbol
VDD
VI
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
ambient temperature
in free air
input transition rise and fall rate
VDD = 5 V
VDD = 10 V
VDD = 15 V
Min Typ Max
3-
15
0-
40 -
VDD
+85
- - 3.75
- - 0.5
- - 0.08
Unit
V
V
C
s/V
s/V
s/V
HEF4557B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 18 November 2011
© NXP B.V. 2011. All rights reserved.
5 of 17
5 Page 
NXP Semiconductors
HEF4557B
1-to-64 bit variable length shift register
a. Input waveforms
VI
negative
pulse
0V
VI
positive
pulse
0V
90 %
10 %
VM
10 %
tf
tr
90 %
VM
tW
90 %
VM
10 %
tr
tf
90 %
VM
10 %
tW 001aaj781
VDD
VI
G
DUT
VO
RT CL
001aag182
b. Test circuit
Fig 6.
Test data is given in Table 11.
Definitions for test circuit:
Device Under Test (DUT)
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Test circuit for switching times
Table 11. Measurement points and test data
Supply voltage
Input
5 V to 15 V
VI
VDD
VM
0.5VI
tr, tf
20 ns
Load
CL
50 pF
HEF4557B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 18 November 2011
© NXP B.V. 2011. All rights reserved.
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